ar71xx: fix ath79_soc_rev value for QCA9531 ver. 2

ath9k expects to get revision id 2 for the QCA9531 ver. 2 rev. 0. This
fixes the very low TX power on some devices like the TP-LINK
TL-WR841ND v10.

As ath79_soc_rev is only used to get the revision number to ath9k on the
QCA9533, just set it to the expected value on the ver. 2.

patches/openwrt/0031-ar71xx-fix-ath79_soc_rev-value-for-QCA9531-ver.-2.patch

+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Thu, 22 Oct 2015 00:33:25 +0200
+Subject: ar71xx: fix ath79_soc_rev value for QCA9531 ver. 2
+
+ath9k expects to get revision id 2 for the QCA9531 ver. 2 rev. 0. This
+fixes the very low TX power on some devices like the TP-LINK
+TL-WR841ND v10.
+
+As ath79_soc_rev is only used to get the revision number to ath9k on the
+QCA9533, just set it to the expected value on the ver. 2.
+
+diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+index d541939..be53a5a 100644
+--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
++++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+@@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  config ATH79_NVRAM
+ --- a/arch/mips/ath79/clock.c
+ +++ b/arch/mips/ath79/clock.c
+-@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(void)
++@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
+  	iounmap(dpll_base);
+  }
+  
+@@ -177,7 +177,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  		platform_device_register(&ath79_uart_device);
+ --- a/arch/mips/ath79/dev-usb.c
+ +++ b/arch/mips/ath79/dev-usb.c
+-@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void)
++@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
+  			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+  }
+  
+@@ -228,7 +228,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  {
+  	return ath79_soc_rev;
+  }
+-@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(void)
++@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
+  		ath79_wmac_data.is_clk_25mhz = true;
+  
+  	if (ath79_soc_rev == 1)
+@@ -237,8 +237,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  
+  	ath79_wmac_data.external_reset = ar933x_wmac_reset;
+  }
+-@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
+- 	ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
++@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
++ 		ath79_wmac_data.is_clk_25mhz = true;
+  }
+  
+ +static void qca953x_wmac_setup(void)
+@@ -264,7 +264,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  static void qca955x_wmac_setup(void)
+  {
+  	u32 t;
+-@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
++@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
+  		ar933x_wmac_setup();
+  	else if (soc_is_ar934x())
+  		ar934x_wmac_setup();
+@@ -286,7 +286,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  		_prom_putchar = prom_putchar_ar71xx;
+ --- a/arch/mips/ath79/gpio.c
+ +++ b/arch/mips/ath79/gpio.c
+-@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_function_reg(void)
++@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
+  	    soc_is_ar913x() ||
+  	    soc_is_ar933x())
+  		reg = AR71XX_GPIO_REG_FUNC;
+@@ -295,7 +295,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  		reg = AR934X_GPIO_REG_FUNC;
+  	else
+  		BUG();
+-@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(unsigned gpio, u8 val)
++@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
+  	unsigned int reg;
+  	u32 t, s;
+  
+@@ -324,7 +324,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  	}
+ --- a/arch/mips/ath79/irq.c
+ +++ b/arch/mips/ath79/irq.c
+-@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(void)
++@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
+  	else if (soc_is_ar724x() ||
+  		 soc_is_ar933x() ||
+  		 soc_is_ar934x() ||
+@@ -405,7 +405,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  }
+ --- a/arch/mips/ath79/setup.c
+ +++ b/arch/mips/ath79/setup.c
+-@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
++@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
+  	u32 major;
+  	u32 minor;
+  	u32 rev = 0;
+@@ -413,12 +413,13 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  
+  	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
+  	major = id & REV_ID_MAJOR_MASK;
+-@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type(void)
++@@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type
+  		rev = id & AR934X_REV_ID_REVISION_MASK;
+  		break;
+  
+ +	case REV_ID_MAJOR_QCA9533_V2:
+ +		ver = 2;
+++		ath79_soc_rev = 2;
+ +		/* drop through */
+ +
+ +	case REV_ID_MAJOR_QCA9533:
+@@ -430,15 +431,23 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+  	case REV_ID_MAJOR_QCA9556:
+  		ath79_soc = ATH79_SOC_QCA9556;
+  		chip = "9556";
+-@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type(void)
++@@ -167,11 +179,12 @@ static void __init ath79_detect_sys_type
++ 		panic("ath79: unknown SoC, id:0x%08x", id);
++ 	}
+  
+- 	ath79_soc_rev = rev;
++-	ath79_soc_rev = rev;
+++	if (ver == 1)
+++		ath79_soc_rev = rev;
+  
+ -	if (soc_is_qca955x())
++-		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++-			chip, rev);
+ +	if (soc_is_qca953x() || soc_is_qca955x())
+- 		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+- 			chip, rev);
+++		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
+++			chip, ver, rev);
+  	else
++ 		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++ 	pr_info("SoC: %s\n", ath79_sys_type);
+ --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+ +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+ @@ -105,6 +105,21 @@
+diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+index 027163f..6e0b536 100644
+--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
++++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+@@ -1,6 +1,6 @@
+ --- a/arch/mips/ath79/Kconfig
+ +++ b/arch/mips/ath79/Kconfig
+-@@ -1213,6 +1213,12 @@ config SOC_QCA955X
++@@ -1248,6 +1248,12 @@ config SOC_QCA955X
+  	select PCI_AR724X if PCI
+  	def_bool n
+  
+@@ -13,7 +13,7 @@
+  config ATH79_DEV_M25P80
+  	select ATH79_DEV_SPI
+  	def_bool n
+-@@ -1250,7 +1256,7 @@ config ATH79_DEV_USB
++@@ -1285,7 +1291,7 @@ config ATH79_DEV_USB
+  	def_bool n
+  
+  config ATH79_DEV_WMAC
+@@ -452,7 +452,7 @@
+  		return -ENODEV;
+ --- a/arch/mips/ath79/setup.c
+ +++ b/arch/mips/ath79/setup.c
+-@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type
++@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
+  		rev = id & QCA955X_REV_ID_REVISION_MASK;
+  		break;
+  
+@@ -471,19 +471,20 @@
+  	default:
+  		panic("ath79: unknown SoC, id:0x%08x", id);
+  	}
+- 
+- 	ath79_soc_rev = rev;
++@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
++ 	if (ver == 1)
++ 		ath79_soc_rev = rev;
+  
+ -	if (soc_is_qca953x() || soc_is_qca955x())
+--		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+ +	if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
+-+		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
+-+			chip, ver, rev);
++ 		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++ 			chip, ver, rev);
+ +	else if (soc_is_tp9343())
+ +		sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
+- 			chip, rev);
+++			chip, rev);
+  	else
+  		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++ 	pr_info("SoC: %s\n", ath79_sys_type);
+ --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+ +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+ @@ -143,6 +143,23 @@