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Unverified Commit a22c1d56 authored by Matthias Schiffer's avatar Matthias Schiffer
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Update OpenWrt base

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patches/openwrt/0054-ar71xx-Use-_eth_cfg-helper-for-Open-Mesh-MR900-boards.patch deleted 100644 → 0
+ 0
− 49
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Tue, 7 Jul 2015 13:47:39 +0000
Subject: ar71xx: Use *_eth_cfg helper for Open Mesh MR900 boards
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r46241
Forwarded: https://patchwork.ozlabs.org/patch/624181/
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
index fe3e1fa..9c3164d 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
@@ -94,24 +94,6 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
},
};
-
-static void __init mr900_gmac_setup(void)
-{
- void __iomem *base;
- u32 t;
-
- base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
-
- t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
-
- t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
- t |= QCA955X_ETH_CFG_RGMII_EN;
-
- __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-
- iounmap(base);
-}
-
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@@ -141,8 +123,7 @@ static void __init mr900_setup(void)
}
pdata->use_eeprom = true;
- mr900_gmac_setup();
-
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
patches/openwrt/0055-ar71xx-Allow-to-use-ath79_gpio_output_select-on-QCA955x.patch deleted 100644 → 0
+ 0
− 79
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Fri, 24 Jul 2015 09:10:00 +0000
Subject: ar71xx: Allow to use ath79_gpio_output_select on QCA955x
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r46459
Forwarded: https://patchwork.ozlabs.org/patch/624182/
diff --git a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
new file mode 100644
index 0000000..e71b6e2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
@@ -0,0 +1,63 @@
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -187,15 +187,30 @@ void __init ath79_gpio_output_select(uns
+ {
+ void __iomem *base = ath79_gpio_base;
+ unsigned long flags;
+- unsigned int reg;
++ unsigned int reg, reg_base;
++ unsigned long gpio_count;
+ u32 t, s;
+
+- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
++ if (soc_is_ar934x()) {
++ gpio_count = AR934X_GPIO_COUNT;
++ reg_base = AR934X_GPIO_REG_OUT_FUNC0;
++ } else if (soc_is_qca953x()) {
++ gpio_count = QCA953X_GPIO_COUNT;
++ reg_base = QCA953X_GPIO_REG_OUT_FUNC0;
++ } else if (soc_is_qca955x()) {
++ gpio_count = QCA955X_GPIO_COUNT;
++ reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
++ } else if (soc_is_qca956x()) {
++ gpio_count = QCA956X_GPIO_COUNT;
++ reg_base = QCA956X_GPIO_REG_OUT_FUNC0;
++ } else {
++ BUG();
++ }
+
+- if (gpio >= AR934X_GPIO_COUNT)
++ if (gpio >= gpio_count)
+ return;
+
+- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
++ reg = reg_base + 4 * (gpio / 4);
+ s = 8 * (gpio % 4);
+
+ spin_lock_irqsave(&ath79_gpio_lock, flags);
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -875,6 +875,14 @@
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+
++#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
++#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
++#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
++#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
++#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
++#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
++#define QCA955X_GPIO_REG_FUNC 0x6c
++
+ #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
+ #define QCA956X_GPIO_REG_OUT_FUNC1 0x30
+ #define QCA956X_GPIO_REG_OUT_FUNC2 0x34
+@@ -1014,6 +1022,8 @@
+ #define AR934X_GPIO_OUT_EXT_LNA0 46
+ #define AR934X_GPIO_OUT_EXT_LNA1 47
+
++#define QCA955X_GPIO_OUT_GPIO 0
++
+ /*
+ * MII_CTRL block
+ */
patches/openwrt/0056-ar71xx-Add-support-for-ath79_gpio_function_-on-QCA955X.patch deleted 100644 → 0
+ 0
− 32
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 23 Mar 2016 12:52:27 +0000
Subject: ar71xx: Add support for ath79_gpio_function_* on QCA955X
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49074
Forwarded: https://patchwork.ozlabs.org/patch/624183/
diff --git a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
index e71b6e2..0e87357 100644
--- a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
@@ -1,6 +1,16 @@
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
-@@ -187,15 +187,30 @@ void __init ath79_gpio_output_select(uns
+@@ -146,7 +146,8 @@ static void __iomem *ath79_gpio_get_func
+ if (soc_is_ar71xx() ||
+ soc_is_ar724x() ||
+ soc_is_ar913x() ||
+- soc_is_ar933x())
++ soc_is_ar933x() ||
++ soc_is_qca955x())
+ reg = AR71XX_GPIO_REG_FUNC;
+ else if (soc_is_ar934x() ||
+ soc_is_qca953x() ||
+@@ -187,15 +188,30 @@ void __init ath79_gpio_output_select(uns
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
patches/openwrt/0057-ar71xx-Add-QCA955X-GPIO-mux-and-function-definitions.patch deleted 100644 → 0
+ 0
− 159
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 23 Mar 2016 12:52:31 +0000
Subject: ar71xx: Add QCA955X GPIO mux and function definitions
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49075
Forwarded: https://patchwork.ozlabs.org/patch/624184/
diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
index 797977f..0126f6a 100644
--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
@@ -194,7 +194,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -529,6 +626,12 @@
+@@ -529,8 +626,22 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -206,8 +206,18 @@
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
++#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
++#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
++#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
++#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
++#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
++#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
++#define QCA955X_GPIO_REG_FUNC 0x6c
++
#define AR71XX_GPIO_COUNT 16
-@@ -560,4 +663,170 @@
+ #define AR7240_GPIO_COUNT 18
+ #define AR7241_GPIO_COUNT 20
+@@ -560,4 +671,235 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -288,6 +298,71 @@
+#define AR934X_GPIO_OUT_EXT_LNA0 46
+#define AR934X_GPIO_OUT_EXT_LNA1 47
+
++#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
++#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
++#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
++#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
++#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
++#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
++#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
++#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
++
++#define QCA955X_GPIO_OUT_GPIO 0
++#define QCA955X_MII_EXT_MDI 1
++#define QCA955X_SLIC_DATA_OUT 3
++#define QCA955X_SLIC_PCM_FS 4
++#define QCA955X_SLIC_PCM_CLK 5
++#define QCA955X_SPI_CLK 8
++#define QCA955X_SPI_CS_0 9
++#define QCA955X_SPI_CS_1 10
++#define QCA955X_SPI_CS_2 11
++#define QCA955X_SPI_MISO 12
++#define QCA955X_I2S_CLK 13
++#define QCA955X_I2S_WS 14
++#define QCA955X_I2S_SD 15
++#define QCA955X_I2S_MCK 16
++#define QCA955X_SPDIF_OUT 17
++#define QCA955X_UART1_TD 18
++#define QCA955X_UART1_RTS 19
++#define QCA955X_UART1_RD 20
++#define QCA955X_UART1_CTS 21
++#define QCA955X_UART0_SOUT 22
++#define QCA955X_SPDIF2_OUT 23
++#define QCA955X_LED_SGMII_SPEED0 24
++#define QCA955X_LED_SGMII_SPEED1 25
++#define QCA955X_LED_SGMII_DUPLEX 26
++#define QCA955X_LED_SGMII_LINK_UP 27
++#define QCA955X_SGMII_SPEED0_INVERT 28
++#define QCA955X_SGMII_SPEED1_INVERT 29
++#define QCA955X_SGMII_DUPLEX_INVERT 30
++#define QCA955X_SGMII_LINK_UP_INVERT 31
++#define QCA955X_GE1_MII_MDO 32
++#define QCA955X_GE1_MII_MDC 33
++#define QCA955X_SWCOM2 38
++#define QCA955X_SWCOM3 39
++#define QCA955X_MAC2_GPIO 40
++#define QCA955X_MAC3_GPIO 41
++#define QCA955X_ATT_LED 42
++#define QCA955X_PWR_LED 43
++#define QCA955X_TX_FRAME 44
++#define QCA955X_RX_CLEAR_EXTERNAL 45
++#define QCA955X_LED_NETWORK_EN 46
++#define QCA955X_LED_POWER_EN 47
++#define QCA955X_WMAC_GLUE_WOW 68
++#define QCA955X_RX_CLEAR_EXTENSION 70
++#define QCA955X_CP_NAND_CS1 73
++#define QCA955X_USB_SUSPEND 74
++#define QCA955X_ETH_TX_ERR 75
++#define QCA955X_DDR_DQ_OE 76
++#define QCA955X_CLKREQ_N_EP 77
++#define QCA955X_CLKREQ_N_RC 78
++#define QCA955X_CLK_OBS0 79
++#define QCA955X_CLK_OBS1 80
++#define QCA955X_CLK_OBS2 81
++#define QCA955X_CLK_OBS3 82
++#define QCA955X_CLK_OBS4 83
++#define QCA955X_CLK_OBS5 84
++
+/*
+ * MII_CTRL block
+ */
diff --git a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
index 0e87357..8a54859 100644
--- a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
@@ -37,37 +37,12 @@
+ }
- if (gpio >= AR934X_GPIO_COUNT)
+- return;
+ if (gpio >= gpio_count)
- return;
++ return;
- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ reg = reg_base + 4 * (gpio / 4);
s = 8 * (gpio % 4);
spin_lock_irqsave(&ath79_gpio_lock, flags);
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -875,6 +875,14 @@
- #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
- #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
-
-+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
-+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
-+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
-+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
-+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
-+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
-+#define QCA955X_GPIO_REG_FUNC 0x6c
-+
- #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
- #define QCA956X_GPIO_REG_OUT_FUNC1 0x30
- #define QCA956X_GPIO_REG_OUT_FUNC2 0x34
-@@ -1014,6 +1022,8 @@
- #define AR934X_GPIO_OUT_EXT_LNA0 46
- #define AR934X_GPIO_OUT_EXT_LNA1 47
-
-+#define QCA955X_GPIO_OUT_GPIO 0
-+
- /*
- * MII_CTRL block
- */
patches/openwrt/0058-ar71xx-Use-PHY-fixups-for-Open-Mesh-MR900.patch deleted 100644 → 0
+ 0
− 78
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 16 Mar 2016 09:27:11 +0000
Subject: ar71xx: Use PHY fixups for Open Mesh MR900
The delays of PHY/MAC on the MR900 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49030
Forwarded: https://patchwork.ozlabs.org/patch/624185/
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
index 9c3164d..3634bf0 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
@@ -23,6 +23,7 @@
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
+#include <linux/platform_data/phy-at803x.h>
#include "common.h"
#include "dev-ap9x-pci.h"
@@ -94,15 +95,30 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
},
};
+static struct at803x_platform_data mr900_at803x_data = {
+ .disable_smarteee = 1,
+ .enable_rgmii_rx_delay = 1,
+ .enable_rgmii_tx_delay = 0,
+ .fixup_rgmii_tx_delay = 1,
+};
+
+static struct mdio_board_info mr900_mdio0_info[] = {
+ {
+ .bus_id = "ag71xx-mdio.0",
+ .phy_addr = 5,
+ .platform_data = &mr900_at803x_data,
+ },
+};
+
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6], pcie_mac[6];
struct ath9k_platform_data *pdata;
- ath79_eth0_pll_data.pll_1000 = 0xbe000101;
- ath79_eth0_pll_data.pll_100 = 0x80000101;
- ath79_eth0_pll_data.pll_10 = 0x80001313;
+ ath79_eth0_pll_data.pll_1000 = 0xae000000;
+ ath79_eth0_pll_data.pll_100 = 0xa0000101;
+ ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_m25p80(NULL);
@@ -126,6 +142,9 @@ static void __init mr900_setup(void)
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
+ mdiobus_register_board_info(mr900_mdio0_info,
+ ARRAY_SIZE(mr900_mdio0_info));
+
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
/* GMAC0 is connected to the RMGII interface */
patches/openwrt/0059-ar71xx-Use-PHY-fixups-for-Open-Mesh-MR1750.patch deleted 100644 → 0
+ 0
− 77
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 16 Mar 2016 09:27:14 +0000
Subject: ar71xx: Use PHY fixups for Open Mesh MR1750
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49031
Forwarded: https://patchwork.ozlabs.org/patch/624186/
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
index 8ace02f..f9e45bd 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
@@ -22,6 +22,7 @@
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
+#include <linux/platform_data/phy-at803x.h>
#include "common.h"
#include "dev-ap9x-pci.h"
@@ -92,14 +93,29 @@ static struct gpio_keys_button mr1750_gpio_keys[] __initdata = {
},
};
+static struct at803x_platform_data mr1750_at803x_data = {
+ .disable_smarteee = 1,
+ .enable_rgmii_rx_delay = 1,
+ .enable_rgmii_tx_delay = 0,
+ .fixup_rgmii_tx_delay = 1,
+};
+
+static struct mdio_board_info mr1750_mdio0_info[] = {
+ {
+ .bus_id = "ag71xx-mdio.0",
+ .phy_addr = 5,
+ .platform_data = &mr1750_at803x_data,
+ },
+};
+
static void __init mr1750_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
- ath79_eth0_pll_data.pll_1000 = 0xbe000101;
- ath79_eth0_pll_data.pll_100 = 0x80000101;
- ath79_eth0_pll_data.pll_10 = 0x80001313;
+ ath79_eth0_pll_data.pll_1000 = 0xae000000;
+ ath79_eth0_pll_data.pll_100 = 0xa0000101;
+ ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_m25p80(NULL);
@@ -116,6 +132,9 @@ static void __init mr1750_setup(void)
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
+ mdiobus_register_board_info(mr1750_mdio0_info,
+ ARRAY_SIZE(mr1750_mdio0_info));
+
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
/* GMAC0 is connected to the RMGII interface */
patches/openwrt/0060-ar71xx-Use-private-version-of-ath79_setup_qca955x_eth_cfg-for-MR900.patch deleted 100644 → 0
+ 0
− 58
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 23 Mar 2016 12:52:09 +0000
Subject: ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR900
The MR900 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR900 can be used instead.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49069
Forwarded: https://patchwork.ozlabs.org/patch/624187/
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
index 3634bf0..b439f58 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
@@ -110,6 +110,28 @@ static struct mdio_board_info mr900_mdio0_info[] = {
},
};
+static void __init mr900_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd,
+ unsigned int rxdv,
+ unsigned int txd,
+ unsigned int txe)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = mask;
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@@ -139,7 +161,7 @@ static void __init mr900_setup(void)
}
pdata->use_eeprom = true;
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr900_mdio0_info,
patches/openwrt/0061-ar71xx-Use-private-version-of-ath79_setup_qca955x_eth_cfg-for-MR1750.patch deleted 100644 → 0
+ 0
− 58
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Wed, 23 Mar 2016 12:52:12 +0000
Subject: ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR1750
The MR1750 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR1750 can be used instead.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49070
Forwarded: https://patchwork.ozlabs.org/patch/624188/
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
index f9e45bd..e3c04e7 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
@@ -108,6 +108,28 @@ static struct mdio_board_info mr1750_mdio0_info[] = {
},
};
+static void __init mr1750_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd,
+ unsigned int rxdv,
+ unsigned int txd,
+ unsigned int txe)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = mask;
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static void __init mr1750_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@@ -129,7 +151,7 @@ static void __init mr1750_setup(void)
ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ mr1750_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr1750_mdio0_info,
patches/openwrt/0062-scripts-om-fwupgradecfg-gen.sh-Fix-u-boot-image-md5sum-check.patch deleted 100644 → 0
+ 0
− 43
View file @ a54e7654
From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Mon, 14 Sep 2015 20:10:10 +0000
Subject: scripts/om-fwupgradecfg-gen.sh: Fix u-boot image md5sum check
The u-boot on Open Mesh devices checks the whole transfered image against a
md5sum. This is stored inside the option filemd5sum inside the
fwupgrade.cfg. The bootloader will not check it when this setting is
missing and could therefore write invalid images to the flash.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r46925
Forwarded: https://patchwork.ozlabs.org/patch/624189/
diff --git a/scripts/om-fwupgradecfg-gen.sh b/scripts/om-fwupgradecfg-gen.sh
index c790214..fab1582 100644
--- a/scripts/om-fwupgradecfg-gen.sh
+++ b/scripts/om-fwupgradecfg-gen.sh
@@ -48,6 +48,7 @@ ROOTFS_FLASH_ADDR=$(addr=$(($KERNEL_FLASH_ADDR + ($KERNEL_PART_SIZE * 1024))); p
ROOTFS_SIZE=$(stat -c%s "$ROOTFS_PATH")
ROOTFS_CHECK_BLOCKS=$((($ROOTFS_SIZE / $CHECK_BS) - $MD5_SKIP_BLOCKS))
ROOTFS_MD5=$(md5=$(dd if=$ROOTFS_PATH bs=$CHECK_BS count=$ROOTFS_CHECK_BLOCKS 2>&- | md5sum); echo ${md5%% *})
+ROOTFS_MD5_FULL=$(md5=$(md5sum $ROOTFS_PATH); echo ${md5%% *})
ROOTFS_CHECK_SIZE=$(printf '0x%x' $(($ROOTFS_CHECK_BLOCKS * $CHECK_BS)))
ROOTFS_PART_SIZE=$(($MAX_PART_SIZE - $KERNEL_PART_SIZE))
@@ -55,6 +56,7 @@ cat << EOF > $CFG_OUT
[vmlinux]
filename=kernel
md5sum=$KERNEL_MD5
+filemd5sum=$KERNEL_MD5
flashaddr=$KERNEL_FLASH_ADDR
checksize=0x0
cmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; saveenv
@@ -63,6 +65,7 @@ cmd_fail=reset
[rootfs]
filename=rootfs
md5sum=$ROOTFS_MD5
+filemd5sum=$ROOTFS_MD5_FULL
flashaddr=$ROOTFS_FLASH_ADDR
checksize=$ROOTFS_CHECK_SIZE
cmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; setenv rootfs_size_1 $ROOTFS_PART_SIZE; saveenv
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