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Commit 6f23ef9e authored by Matthias Schiffer's avatar Matthias Schiffer
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Update OpenWrt base 

We got most of our patches backported by upstream :)
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GLUON_FEEDS='openwrt gluon routing luci'
OPENWRT_REPO=git://git.openwrt.org/15.05/openwrt.git
OPENWRT_COMMIT=a03a846c49c067048cd225d476a7adf91ef8ff03
OPENWRT_COMMIT=8882c524d9b5e4c16ebfea10c0090f38b07c9da5
PACKAGES_OPENWRT_REPO=git://github.com/openwrt/packages.git
PACKAGES_OPENWRT_COMMIT=9622fe984bba3a4547f48bc507ebaba7637eb2b0
......
patches/openwrt/0008-ath10k-firmware-add-Candela-Technologies-firmware-for-QCA988X.patch → patches/openwrt/0006-ath10k-firmware-add-Candela-Technologies-firmware-for-QCA988X.patch
+ 4
− 4
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......@@ -3,10 +3,10 @@ Date: Tue, 9 Feb 2016 18:22:29 +0100
Subject: ath10k-firmware: add Candela Technologies firmware for QCA988X
diff --git a/package/firmware/ath10k-firmware/Makefile b/package/firmware/ath10k-firmware/Makefile
index 882294c..c6e6f2d 100644
index b03d644..7d4d449 100644
--- a/package/firmware/ath10k-firmware/Makefile
+++ b/package/firmware/ath10k-firmware/Makefile
@@ -46,6 +46,26 @@ define Download/ath10k-firmware-qca988x
@@ -44,6 +44,26 @@ define Download/ath10k-firmware-qca988x
endef
$(eval $(call Download,ath10k-firmware-qca988x))
......@@ -33,7 +33,7 @@ index 882294c..c6e6f2d 100644
define Package/ath10k-firmware-qca99x0
$(Package/ath10k-firmware-default)
TITLE:=ath10k firmware for QCA99x0 devices
@@ -81,6 +101,16 @@ define Package/ath10k-firmware-qca988x/install
@@ -79,6 +99,16 @@ define Package/ath10k-firmware-qca988x/install
$(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin
endef
......@@ -50,7 +50,7 @@ index 882294c..c6e6f2d 100644
define Package/ath10k-firmware-qca6174/install
$(INSTALL_DIR) $(1)/lib/firmware/ath10k
$(CP) $(PKG_BUILD_DIR)/QCA6174 $(1)/lib/firmware/ath10k/
@@ -100,5 +130,6 @@ define Package/ath10k-firmware-qca99x0/install
@@ -98,5 +128,6 @@ define Package/ath10k-firmware-qca99x0/install
endef
$(eval $(call BuildPackage,ath10k-firmware-qca988x))
......
patches/openwrt/0006-build-add-support-for-choosing-a-different-url-filename-part-than-the-output-file.patch deleted 100644 → 0
+ 0
− 68
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Tue, 9 Feb 2016 13:49:01 +0100
Subject: build: add support for choosing a different url filename part than the output file
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Backport of r47591 and r48427
diff --git a/include/download.mk b/include/download.mk
index 937b5d3..e518cce 100644
--- a/include/download.mk
+++ b/include/download.mk
@@ -44,11 +44,11 @@ define DownloadMethod/unknown
endef
define DownloadMethod/default
- $(SCRIPT_DIR)/download.pl "$(DL_DIR)" "$(FILE)" "$(MD5SUM)" $(foreach url,$(URL),"$(url)")
+ $(SCRIPT_DIR)/download.pl "$(DL_DIR)" "$(FILE)" "$(MD5SUM)" "$(URL_FILE)" $(foreach url,$(URL),"$(url)")
endef
define wrap_mirror
- $(if $(if $(MIRROR),$(filter-out x,$(MIRROR_MD5SUM))),@$(SCRIPT_DIR)/download.pl "$(DL_DIR)" "$(FILE)" "$(MIRROR_MD5SUM)" || ( $(1) ),$(1))
+ $(if $(if $(MIRROR),$(filter-out x,$(MIRROR_MD5SUM))),@$(SCRIPT_DIR)/download.pl "$(DL_DIR)" "$(FILE)" "$(MIRROR_MD5SUM)" "" || ( $(1) ),$(1))
endef
define DownloadMethod/cvs
@@ -157,6 +157,7 @@ Validate/darcs=VERSION SUBDIR
define Download/Defaults
URL:=
FILE:=
+ URL_FILE:=
PROTO:=
MD5SUM:=
SUBDIR:=
diff --git a/scripts/download.pl b/scripts/download.pl
index cd68a7b..111d03c 100755
--- a/scripts/download.pl
+++ b/scripts/download.pl
@@ -11,15 +11,19 @@ use warnings;
use File::Basename;
use File::Copy;
-@ARGV > 2 or die "Syntax: $0 <target dir> <filename> <md5sum> [<mirror> ...]\n";
+@ARGV > 2 or die "Syntax: $0 <target dir> <filename> <md5sum> <url filename> [<mirror> ...]\n";
+my $url_filename;
my $target = shift @ARGV;
my $filename = shift @ARGV;
my $md5sum = shift @ARGV;
+$url_filename = shift @ARGV unless $ARGV[0] =~ /:\/\//;
my $scriptdir = dirname($0);
my @mirrors;
my $ok;
+$url_filename or $url_filename = $filename;
+
sub localmirrors {
my @mlist;
open LM, "$scriptdir/localmirrors" and do {
@@ -106,7 +110,7 @@ sub download
return;
}
} else {
- open WGET, "wget -t5 --timeout=20 --no-check-certificate $options -O- '$mirror/$filename' |" or die "Cannot launch wget.\n";
+ open WGET, "wget -t5 --timeout=20 --no-check-certificate $options -O- '$mirror/$url_filename' |" or die "Cannot launch wget.\n";
open MD5SUM, "| $md5cmd > '$target/$filename.md5sum'" or die "Cannot launch md5sum.\n";
open OUTPUT, "> $target/$filename.dl" or die "Cannot create file $target/$filename.dl: $!\n";
my $buffer;
patches/openwrt/0007-mac80211-backport-from-trunk-r48810.patch deleted 100644 → 0
+ 0
− 33113
View file @ 289b5992
Source diff could not be displayed: it is too large. Options to address this: view the blob.
patches/openwrt/0011-ar71xx-add-support-for-tp-link-wr740n-v5.0-EU.patch deleted 100644 → 0
+ 0
− 39
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Sun, 21 Jun 2015 22:50:48 +0200
Subject: ar71xx: add support for tp-link wr740n v5.0 (EU)
TP-Link ships wr740n v5.0 to Romania (so probably everywhere except
China) with 4 MB flash and 32 MB memory (confirmed by their local
support). This patch adds support for the v5.0 clone of v4, i just
tested it on my own v5.0 router and it works.
Signed-off-by: Daniel Petre <daniel.petre@posteo.net>
diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile
index 4336697..1fe88d5 100644
--- a/target/linux/ar71xx/image/Makefile
+++ b/target/linux/ar71xx/image/Makefile
@@ -501,6 +501,14 @@ define Device/tl-wr740n-v4
CONSOLE := ttyATH0,115200
endef
+define Device/tl-wr740n-v5
+ $(Device/tplink-4mlzma)
+ BOARDNAME := TL-WR741ND-v4
+ DEVICE_PROFILE := TLWR740
+ TPLINK_HWID := 0x07400005
+ CONSOLE := ttyATH0,115200
+endef
+
define Device/tl-wr741nd-v1
$(Device/tplink-4m)
BOARDNAME := TL-WR741ND
@@ -530,7 +538,7 @@ define Device/tl-wr743nd-v2
TPLINK_HWID := 0x07430002
CONSOLE := ttyATH0,115200
endef
-TARGET_DEVICES += tl-wr740n-v4 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr743nd-v2
+TARGET_DEVICES += tl-wr740n-v4 tl-wr740n-v5 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr743nd-v2
define Device/tl-wr841n-v8
$(Device/tplink-4mlzma)
patches/openwrt/0012-ar71xx-add-support-for-TL-WR741ND-v5.patch deleted 100644 → 0
+ 0
− 35
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Sun, 21 Jun 2015 22:48:04 +0200
Subject: ar71xx: add support for TL-WR741ND v5
This device is identical to the TL-WR740N v5, it even uses the same HWID (which
wasn't the case for older TL-WR741ND revisions).
diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile
index 1fe88d5..78d35e1 100644
--- a/target/linux/ar71xx/image/Makefile
+++ b/target/linux/ar71xx/image/Makefile
@@ -531,6 +531,14 @@ define Device/tl-wr741nd-v4
CONSOLE := ttyATH0,115200
endef
+define Device/tl-wr741nd-v5
+ $(Device/tplink-4mlzma)
+ BOARDNAME := TL-WR741ND-v4
+ DEVICE_PROFILE := TLWR741
+ TPLINK_HWID := 0x07400005
+ CONSOLE := ttyATH0,115200
+endef
+
define Device/tl-wr743nd-v2
$(Device/tplink-4mlzma)
BOARDNAME := TL-WR741ND-v4
@@ -538,7 +546,7 @@ define Device/tl-wr743nd-v2
TPLINK_HWID := 0x07430002
CONSOLE := ttyATH0,115200
endef
-TARGET_DEVICES += tl-wr740n-v4 tl-wr740n-v5 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr743nd-v2
+TARGET_DEVICES += tl-wr740n-v4 tl-wr740n-v5 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr741nd-v5 tl-wr743nd-v2
define Device/tl-wr841n-v8
$(Device/tplink-4mlzma)
patches/openwrt/0013-sunxi-fix-uboot-install-location.patch deleted 100644 → 0
+ 0
− 131
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Thu, 16 Jul 2015 22:01:02 +0200
Subject: sunxi: fix uboot install location
Install uboot files to KERNEL_BUILD_DIR instead of BIN_DIR to fix the
ImageBuilder. Similar fixes are necessary for many (all?) other uboot
targets.
Also remove the DTS copy command, BIN_DIR was unnecessarily cluttered with
DTS files unrelated to the chosen profile.
diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile
index 14ba922..9032600 100644
--- a/package/boot/uboot-sunxi/Makefile
+++ b/package/boot/uboot-sunxi/Makefile
@@ -6,6 +6,7 @@
#
include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot
PKG_VERSION:=2015.01
@@ -16,7 +17,7 @@ PKG_SOURCE_URL:= \
PKG_MD5SUM:=7f08dc9e98a71652bd6968888ed6ec95
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_LICENSE:=GPL-2.0 GPL-2.0+
PKG_LICENSE_FILES:=Licenses/README
@@ -136,16 +137,16 @@ define Build/Compile
endef
define Package/uboot/install/default
- $(INSTALL_DIR) $(BIN_DIR)/uboot-$(BOARD)-$(1)
$(CP) $(PKG_BUILD_DIR)/u-boot.bin \
- $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot.bin
+ $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-u-boot.bin
$(CP) $(PKG_BUILD_DIR)/spl/sunxi-spl.bin \
- $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-spl.bin
+ $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-spl.bin
$(CP) $(PKG_BUILD_DIR)/u-boot-sunxi-with-spl.bin \
- $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot-with-spl.bin
+ $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-u-boot-with-spl.bin
$(CP) uEnv.txt \
- $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-uEnv.txt
- mkimage -C none -A arm -T script -d $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-uEnv.txt $(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-boot.scr
+ $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-uEnv.txt
+ mkimage -C none -A arm -T script -d $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-uEnv.txt \
+ $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-boot.scr
endef
define Package/uboot/install/template
diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile
index 6fcd61f..19ab935 100644
--- a/target/linux/sunxi/image/Makefile
+++ b/target/linux/sunxi/image/Makefile
@@ -11,28 +11,12 @@ include $(INCLUDE_DIR)/host.mk
FAT32_BLOCK_SIZE=1024
FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SUNXI_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))
-BOARDS:= \
- sun4i-a10-cubieboard \
- sun4i-a10-olinuxino-lime \
- sun4i-a10-pcduino \
- sun5i-a13-olinuxino \
- sun6i-a31-colombus \
- sun6i-a31-m9 \
- sun7i-a20-bananapi \
- sun7i-a20-bananapro \
- sun7i-a20-cubieboard2 \
- sun7i-a20-cubietruck \
- sun7i-a20-olinuxino-lime \
- sun7i-a20-olinuxino-micro \
- sun7i-a20-pcduino3 \
- sun7i-a20-lamobo-r1
-
define Image/BuildKernel
mkimage -A arm -O linux -T kernel -C none \
-a 0x40008000 -e 0x40008000 \
-n 'ARM OpenWrt Linux-$(LINUX_VERSION)' \
-d $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-
+
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
$(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
echo -ne '\x00\x00\x00\x00' >> $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
@@ -42,27 +26,23 @@ define Image/BuildKernel
$(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \
)
endif
-
- $(foreach board,$(BOARDS),
- $(CP) $(DTS_DIR)/$(board).dtb $(BIN_DIR)/
- )
endef
define Image/Build/SDCard
rm -f $(KDIR)/boot.img
mkdosfs $(KDIR)/boot.img -C $(FAT32_BLOCKS)
-
- mcopy -i $(KDIR)/boot.img $(BIN_DIR)/uboot-sunxi-$(PROFILE)/$(IMG_PREFIX)-$(PROFILE)-boot.scr ::boot.scr
- mcopy -i $(KDIR)/boot.img $(BIN_DIR)/$(2).dtb ::dtb
+
+ mcopy -i $(KDIR)/boot.img $(KDIR)/uboot-sunxi-$(PROFILE)-boot.scr ::boot.scr
+ mcopy -i $(KDIR)/boot.img $(DTS_DIR)/$(2).dtb ::dtb
mcopy -i $(KDIR)/boot.img $(BIN_DIR)/$(IMG_PREFIX)-uImage ::uImage
-
+
./gen_sunxi_sdcard_img.sh \
$(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-sdcard-vfat-$(1).img \
$(KDIR)/boot.img \
$(KDIR)/root.$(1) \
$(CONFIG_SUNXI_SD_BOOT_PARTSIZE) \
$(CONFIG_TARGET_ROOTFS_PARTSIZE) \
- $(BIN_DIR)/uboot-sunxi-$(PROFILE)/$(IMG_PREFIX)-$(PROFILE)-u-boot-with-spl.bin
+ $(KDIR)/uboot-sunxi-$(PROFILE)-u-boot-with-spl.bin
endef
define Image/Build/Profile/A10-OLinuXino-Lime
@@ -124,7 +104,7 @@ endef
define Image/Build
$(call Image/Build/$(1),$(1))
$(call Image/Build/Profile/$(PROFILE),$(1))
-
+
dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
endef
patches/openwrt/0014-sunxi-respect-CONFIG_TARGET_IMAGES_GZIP.patch deleted 100644 → 0
+ 0
− 21
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Thu, 16 Jul 2015 22:13:59 +0200
Subject: sunxi: respect CONFIG_TARGET_IMAGES_GZIP
The ext4 images are huge uncompressed.
diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile
index 19ab935..d3f4409 100644
--- a/target/linux/sunxi/image/Makefile
+++ b/target/linux/sunxi/image/Makefile
@@ -43,6 +43,10 @@ define Image/Build/SDCard
$(CONFIG_SUNXI_SD_BOOT_PARTSIZE) \
$(CONFIG_TARGET_ROOTFS_PARTSIZE) \
$(KDIR)/uboot-sunxi-$(PROFILE)-u-boot-with-spl.bin
+
+ ifneq ($(CONFIG_TARGET_IMAGES_GZIP),)
+ gzip -f9n $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-sdcard-vfat-$(1).img
+ endif
endef
define Image/Build/Profile/A10-OLinuXino-Lime
patches/openwrt/0015-odhcp6c-add-option-sourcefilter-to-disable-source-filter.patch deleted 100644 → 0
+ 0
− 62
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Sat, 18 Jul 2015 17:13:23 +0200
Subject: odhcp6c: add option "sourcefilter" to disable source filter
Signed-off-by: Steven Barth <steven@midlink.org>
diff --git a/package/network/ipv6/odhcp6c/Makefile b/package/network/ipv6/odhcp6c/Makefile
index 5bf43bd..75de54c 100644
--- a/package/network/ipv6/odhcp6c/Makefile
+++ b/package/network/ipv6/odhcp6c/Makefile
@@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=odhcp6c
-PKG_VERSION:=2015-07-13
+PKG_VERSION:=2015-07-18
PKG_RELEASE=$(PKG_SOURCE_VERSION)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
diff --git a/package/network/ipv6/odhcp6c/files/dhcpv6.script b/package/network/ipv6/odhcp6c/files/dhcpv6.script
index b8cbddb..33f6d9b 100755
--- a/package/network/ipv6/odhcp6c/files/dhcpv6.script
+++ b/package/network/ipv6/odhcp6c/files/dhcpv6.script
@@ -76,7 +76,7 @@ setup_interface () {
done
for entry in $RA_ROUTES; do
- local duplicate=0
+ local duplicate=$NOSOURCEFILTER
local addr="${entry%%/*}"
entry="${entry#*/}"
local mask="${entry%%,*}"
diff --git a/package/network/ipv6/odhcp6c/files/dhcpv6.sh b/package/network/ipv6/odhcp6c/files/dhcpv6.sh
index adcb100..4a453fd 100755
--- a/package/network/ipv6/odhcp6c/files/dhcpv6.sh
+++ b/package/network/ipv6/odhcp6c/files/dhcpv6.sh
@@ -28,14 +28,15 @@ proto_dhcpv6_init_config() {
proto_config_add_boolean delegate
proto_config_add_int "soltimeout"
proto_config_add_boolean fakeroutes
+ proto_config_add_boolean sourcefilter
}
proto_dhcpv6_setup() {
local config="$1"
local iface="$2"
- local reqaddress reqprefix clientid reqopts noslaaconly forceprefix norelease ip6prefix iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone soltimeout fakeroutes
- json_get_vars reqaddress reqprefix clientid reqopts noslaaconly forceprefix norelease ip6prefix iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone soltimeout fakeroutes
+ local reqaddress reqprefix clientid reqopts noslaaconly forceprefix norelease ip6prefix iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone soltimeout fakeroutes sourcefilter
+ json_get_vars reqaddress reqprefix clientid reqopts noslaaconly forceprefix norelease ip6prefix iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone soltimeout fakeroutes sourcefilter
# Configure
@@ -76,6 +77,7 @@ proto_dhcpv6_setup() {
[ -n "$zone_464xlat" ] && proto_export "ZONE_464XLAT=$zone_464xlat"
[ -n "$zone" ] && proto_export "ZONE=$zone"
[ "$fakeroutes" != "0" ] && proto_export "FAKE_ROUTES=1"
+ [ "$sourcefilter" = "0" ] && proto_export "NOSOURCEFILTER=1"
proto_export "INTERFACE=$config"
proto_run_command "$config" odhcp6c \
patches/openwrt/0017-ar71xx-fix-ethernet-initialization-on-QCA953x-based-boards-TP-Link-TL-WR841N-ND-v9-Compex-WPJ531.patch deleted 100644 → 0
+ 0
− 57
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Thu, 6 Aug 2015 03:01:38 +0200
Subject: ar71xx: fix ethernet initialization on QCA953x-based boards (TP-Link TL-WR841N/ND v9, Compex WPJ531)
The initialization routines for these boards were relying on some (wrong)
defaults for the QCA953x ethernet. Make these defaults explicit to prevent
breaking them when the QCA953x defaults are fixed.
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
index c28afc6..3e5c2a2 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
@@ -109,12 +109,18 @@ static void __init tl_ap143_setup(void)
ath79_register_mdio(0, 0x0);
/* LAN */
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+ ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
index bc13d70..e665a2e 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
@@ -105,12 +105,19 @@ static void __init common_setup(void)
ath79_register_mdio(0, 0x0);
/* LAN */
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth1_data.speed = SPEED_100;
+ ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_eth(1);
patches/openwrt/0018-ar71xx-rework-patch-for-qca953x-956x.patch deleted 100644 → 0
+ 0
− 807
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Thu, 6 Aug 2015 03:01:47 +0200
Subject: ar71xx: rework patch for qca953x/956x
Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e
Changelist,
- add more register defines
- add EHCI support
- fix GPIO pin count to 18
- fix chained irq disabled
- fix GMAC0/GMAC1 initial
- fix WMAC irq number to 47
- merge the changes of dev-eth.c from the patch to file.
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index ae3db4c..ff94e2e 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
mdio_dev = &ath79_mdio1_device;
mdio_data = &ath79_mdio1_data;
break;
@@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
break;
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
mdio_data->builtin_switch = 1;
break;
@@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
case ATH79_SOC_QCA9533:
case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pll_10 = AR934X_PLL_VAL_10;
pll_100 = AR934X_PLL_VAL_100;
pll_1000 = AR934X_PLL_VAL_1000;
@@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
break;
@@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR7241:
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
break;
@@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9533:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id)
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9533:
if (id == 0) {
pdata->reset_bit = AR934X_RESET_GE0_MAC |
AR934X_RESET_GE0_MDIO;
@@ -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id)
pdata->fifo_cfg3 = 0x01f00140;
break;
- case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
if (id == 0) {
pdata->reset_bit = AR933X_RESET_GE0_MAC |
AR933X_RESET_GE0_MDIO;
@@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id)
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
break;
diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index f3b4446..cf10af3 100644
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -175,6 +175,48 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
soc_is_qca955x()) {
ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device);
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+
++static void __init qca953x_usb_setup(void)
++{
++ u32 bootstrap;
++
++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++
++ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
++ udelay(1000);
++
++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
++ udelay(1000);
++
++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
++ udelay(1000);
++
++ ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
++ udelay(1000);
++
++ ath79_usb_register("ehci-platform", -1,
++ QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
++ ATH79_CPU_IRQ(3),
++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ static void qca955x_usb_reset_notifier(struct platform_device *pdev)
+ {
+ u32 base;
+@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
+ ar933x_usb_setup();
+ else if (soc_is_ar934x())
+ ar934x_usb_setup();
++ else if (soc_is_qca953x())
++ qca953x_usb_setup();
+ else if (soc_is_qca955x())
+ qca955x_usb_setup();
+ else
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
@@ -207,8 +249,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+
+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
+ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
-+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
+
+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
@@ -244,6 +286,24 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
_prom_putchar = prom_putchar_ar71xx;
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
+ soc_is_ar913x() ||
+ soc_is_ar933x())
+ reg = AR71XX_GPIO_REG_FUNC;
+- else if (soc_is_ar934x())
++ else if (soc_is_ar934x() || soc_is_qca953x())
+ reg = AR934X_GPIO_REG_FUNC;
+ else
+ BUG();
+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
+ unsigned int reg;
+ u32 t, s;
+
+- BUG_ON(!soc_is_ar934x());
++ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
+
+ if (gpio >= AR934X_GPIO_COUNT)
+ return;
@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
ath79_gpio_count = AR933X_GPIO_COUNT;
else if (soc_is_ar934x())
@@ -272,16 +332,77 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
soc_is_qca955x())
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
else
-@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
+@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+
++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++ u32 status;
++
++ disable_irq_nosync(irq);
++
++ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
++
++ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
++ generic_handle_irq(ATH79_IP2_IRQ(0));
++ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
++ generic_handle_irq(ATH79_IP2_IRQ(1));
++ } else {
++ spurious_interrupt();
++ }
++
++ enable_irq(irq);
++}
++
++static void qca953x_irq_init(void)
++{
++ int i;
++
++ for (i = ATH79_IP2_IRQ_BASE;
++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
++}
++
+ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+ {
+ u32 status;
+@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
+ do_IRQ(ATH79_CPU_IRQ(3));
+ }
+
++static void qca953x_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ void __init arch_init_irq(void)
+ {
+ if (soc_is_ar71xx()) {
+@@ -352,6 +391,9 @@ void __init arch_init_irq(void)
} else if (soc_is_ar934x()) {
ath79_ip2_handler = ath79_default_ip2_handler;
ath79_ip3_handler = ar934x_ip3_handler;
+ } else if (soc_is_qca953x()) {
+ ath79_ip2_handler = ath79_default_ip2_handler;
-+ ath79_ip3_handler = ath79_default_ip3_handler;
++ ath79_ip3_handler = qca953x_ip3_handler;
} else if (soc_is_qca955x()) {
ath79_ip2_handler = ath79_default_ip2_handler;
ath79_ip3_handler = ath79_default_ip3_handler;
+@@ -365,6 +407,8 @@ void __init arch_init_irq(void)
+
+ if (soc_is_ar934x())
+ ar934x_ip2_irq_init();
++ else if (soc_is_qca953x())
++ qca953x_irq_init();
+ else if (soc_is_qca955x())
+ qca955x_irq_init();
+ }
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
@@ -329,23 +450,49 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -105,6 +105,9 @@
+@@ -105,6 +105,21 @@
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
#define AR934X_SRIF_SIZE 0x1000
++#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
++#define QCA953X_GMAC_SIZE 0x14
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE 0x20000
++#define QCA953X_EHCI_BASE 0x1b000000
++#define QCA953X_EHCI_SIZE 0x200
++#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
++#define QCA953X_SRIF_SIZE 0x1000
++
++#define QCA953X_PCI_CFG_BASE0 0x14000000
++#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
++#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA953X_PCI_MEM_BASE0 0x10000000
++#define QCA953X_PCI_MEM_SIZE 0x02000000
+
#define QCA955X_PCI_MEM_BASE0 0x10000000
#define QCA955X_PCI_MEM_BASE1 0x12000000
#define QCA955X_PCI_MEM_SIZE 0x02000000
-@@ -279,6 +282,43 @@
+@@ -173,6 +188,12 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC 0xac
+
++#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
++#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
++#define QCA953X_DDR_REG_FLUSH_USB 0xa4
++#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
++#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
++
+ /*
+ * PLL block
+ */
+@@ -279,6 +300,44 @@
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
+
@@ -356,7 +503,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
@@ -383,27 +530,85 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -355,6 +395,10 @@
+@@ -355,6 +414,10 @@
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
-+#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac
++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
-@@ -503,6 +547,8 @@
+@@ -450,6 +513,27 @@
+ #define AR934X_RESET_MBOX BIT(1)
+ #define AR934X_RESET_I2S BIT(0)
+
++#define QCA953X_RESET_USB_EXT_PWR BIT(29)
++#define QCA953X_RESET_EXTERNAL BIT(28)
++#define QCA953X_RESET_RTC BIT(27)
++#define QCA953X_RESET_FULL_CHIP BIT(24)
++#define QCA953X_RESET_GE1_MDIO BIT(23)
++#define QCA953X_RESET_GE0_MDIO BIT(22)
++#define QCA953X_RESET_CPU_NMI BIT(21)
++#define QCA953X_RESET_CPU_COLD BIT(20)
++#define QCA953X_RESET_DDR BIT(16)
++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA953X_RESET_GE1_MAC BIT(13)
++#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
++#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
++#define QCA953X_RESET_GE0_MAC BIT(9)
++#define QCA953X_RESET_ETH_SWITCH BIT(8)
++#define QCA953X_RESET_PCIE_PHY BIT(7)
++#define QCA953X_RESET_PCIE BIT(6)
++#define QCA953X_RESET_USB_HOST BIT(5)
++#define QCA953X_RESET_USB_PHY BIT(4)
++#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
++
+ #define QCA955X_RESET_HOST BIT(31)
+ #define QCA955X_RESET_SLIC BIT(30)
+ #define QCA955X_RESET_HDMA BIT(29)
+@@ -503,6 +587,13 @@
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
++#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
++#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
++#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
+
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
-@@ -565,6 +611,8 @@
+@@ -523,6 +614,24 @@
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
++#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
++ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
++ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
++
++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
++ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
++ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
++ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
++
+ #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
+ #define QCA955X_EXT_INT_WMAC_TX BIT(1)
+ #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
+@@ -565,6 +674,8 @@
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
@@ -412,7 +617,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
-@@ -587,6 +635,8 @@
+@@ -587,6 +698,8 @@
#define AR934X_REV_ID_REVISION_MASK 0xf
@@ -421,14 +626,81 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_REV_ID_REVISION_MASK 0xf
/*
-@@ -640,6 +690,7 @@
+@@ -634,12 +747,32 @@
+ #define AR934X_GPIO_REG_OUT_FUNC5 0x40
+ #define AR934X_GPIO_REG_FUNC 0x6c
+
++#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
++#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
++#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
++#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
++#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
++#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
++#define QCA953X_GPIO_REG_FUNC 0x6c
++
++#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
++#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
++#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
++#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
++#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
++#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
++#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
++#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
++#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
++
+ #define AR71XX_GPIO_COUNT 16
+ #define AR7240_GPIO_COUNT 18
+ #define AR7241_GPIO_COUNT 20
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
-+#define QCA953X_GPIO_COUNT 24
++#define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24
/*
+@@ -663,6 +796,24 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
++#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
++#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
++#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
++
++#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
++#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
++#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
++
++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
++#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
++#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
++#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
++#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
++
++#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
++
+ #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
+ #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
+ #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
+@@ -804,6 +955,16 @@
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+ /*
++ * QCA953X GMAC Interface
++ */
++#define QCA953X_GMAC_REG_ETH_CFG 0x00
++
++#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
++#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
++#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
++
++/*
+ * QCA955X GMAC Interface
+ */
+
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -32,6 +32,7 @@ enum ath79_soc_type {
diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index ab2bc38..eecccdc 100644
--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -142,74 +142,9 @@
ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
---- a/arch/mips/ath79/dev-eth.c
-+++ b/arch/mips/ath79/dev-eth.c
-@@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned
- case ATH79_SOC_AR9330:
- case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- mdio_dev = &ath79_mdio1_device;
- mdio_data = &ath79_mdio1_data;
- break;
-@@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned
- break;
-
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- mdio_data->builtin_switch = 1;
- break;
-
-@@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_da
- case ATH79_SOC_QCA9533:
- case ATH79_SOC_QCA9556:
- case ATH79_SOC_QCA9558:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- pll_10 = AR934X_PLL_VAL_10;
- pll_100 = AR934X_PLL_VAL_100;
- pll_1000 = AR934X_PLL_VAL_1000;
-@@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mod
- case ATH79_SOC_AR9330:
- case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
- break;
-
-@@ -688,6 +696,8 @@ static int __init ath79_setup_phy_if_mod
- case ATH79_SOC_AR9330:
- case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
- break;
-
-@@ -1018,6 +1028,8 @@ void __init ath79_register_eth(unsigned
- break;
-
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- if (id == 0) {
- pdata->reset_bit = AR933X_RESET_GE0_MAC |
- AR933X_RESET_GE0_MDIO;
-@@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned
- case ATH79_SOC_AR9330:
- case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
-+ case ATH79_SOC_QCA9561:
-+ case ATH79_SOC_TP9343:
- pdata->mii_bus_dev = &ath79_mdio1_device.dev;
- break;
-
--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
-@@ -272,6 +272,19 @@ static void __init qca955x_usb_setup(voi
+@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
}
@@ -229,8 +164,8 @@
void __init ath79_register_usb(void)
{
if (soc_is_ar71xx())
-@@ -288,6 +301,8 @@ void __init ath79_register_usb(void)
- ar934x_usb_setup();
+@@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
+ qca953x_usb_setup();
else if (soc_is_qca955x())
qca955x_usb_setup();
+ else if (soc_is_qca9561())
@@ -291,9 +226,9 @@
soc_is_ar913x() ||
soc_is_ar933x())
reg = AR71XX_GPIO_REG_FUNC;
-- else if (soc_is_ar934x())
+- else if (soc_is_ar934x() || soc_is_qca953x())
+ else if (soc_is_ar934x() ||
-+ soc_is_qca956x())
++ soc_is_qca953x() || soc_is_qca956x())
reg = AR934X_GPIO_REG_FUNC;
else
BUG();
@@ -326,7 +261,7 @@
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
else
BUG();
-@@ -236,6 +237,99 @@ static void qca955x_irq_init(void)
+@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
}
@@ -406,15 +341,13 @@
+
+ for (i = ATH79_IP2_IRQ_BASE;
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip,
-+ handle_level_irq);
++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
+
+ for (i = ATH79_IP3_IRQ_BASE;
+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip,
-+ handle_level_irq);
++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+
+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
+
@@ -426,7 +359,7 @@
asmlinkage void plat_irq_dispatch(void)
{
unsigned long pending;
-@@ -359,6 +453,9 @@ void __init arch_init_irq(void)
+@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
} else if (soc_is_qca955x()) {
ath79_ip2_handler = ath79_default_ip2_handler;
ath79_ip3_handler = ath79_default_ip3_handler;
@@ -436,8 +369,8 @@
} else {
BUG();
}
-@@ -371,4 +468,6 @@ void __init arch_init_irq(void)
- ar934x_ip2_irq_init();
+@@ -411,4 +506,6 @@ void __init arch_init_irq(void)
+ qca953x_irq_init();
else if (soc_is_qca955x())
qca955x_irq_init();
+ else if (soc_is_qca956x())
@@ -554,7 +487,7 @@
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -131,6 +131,23 @@
+@@ -143,6 +143,23 @@
#define QCA955X_NFC_BASE 0x1b800200
#define QCA955X_NFC_SIZE 0xb8
@@ -578,7 +511,7 @@
#define AR9300_OTP_BASE 0x14000
#define AR9300_OTP_STATUS 0x15f18
#define AR9300_OTP_STATUS_TYPE 0x7
-@@ -356,6 +373,49 @@
+@@ -375,6 +392,49 @@
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@@ -628,7 +561,7 @@
/*
* USB_CONFIG block
*/
-@@ -403,6 +463,11 @@
+@@ -422,6 +482,11 @@
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
@@ -640,7 +573,7 @@
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
-@@ -551,6 +616,8 @@
+@@ -596,6 +661,8 @@
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
@@ -649,7 +582,7 @@
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
-@@ -600,6 +667,37 @@
+@@ -663,6 +730,37 @@
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
QCA955X_EXT_INT_PCIE_RC2_INT3)
@@ -687,7 +620,7 @@
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
-@@ -615,6 +713,8 @@
+@@ -678,6 +776,8 @@
#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
@@ -696,7 +629,7 @@
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
-@@ -639,6 +739,8 @@
+@@ -702,6 +802,8 @@
#define QCA955X_REV_ID_REVISION_MASK 0xf
@@ -705,9 +638,9 @@
/*
* SPI block
*/
-@@ -684,6 +786,19 @@
- #define AR934X_GPIO_REG_OUT_FUNC5 0x40
- #define AR934X_GPIO_REG_FUNC 0x6c
+@@ -766,6 +868,19 @@
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
@@ -725,9 +658,9 @@
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -692,6 +807,7 @@
+@@ -774,6 +889,7 @@
#define AR934X_GPIO_COUNT 23
- #define QCA953X_GPIO_COUNT 24
+ #define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24
+#define QCA956X_GPIO_COUNT 23
diff --git a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
index 8cb38d3..8c0cc95 100644
--- a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
+++ b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
@@ -19,7 +19,16 @@
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
}
-@@ -224,15 +225,13 @@ static void qca955x_irq_init(void)
+@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
+
+ for (i = ATH79_IP2_IRQ_BASE;
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
+ }
+@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
@@ -37,25 +46,23 @@
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
}
-@@ -313,15 +312,13 @@ static void qca956x_irq_init(void)
+@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
for (i = ATH79_IP2_IRQ_BASE;
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip,
-- handle_level_irq);
+- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
for (i = ATH79_IP3_IRQ_BASE;
i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip,
-- handle_level_irq);
+- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
-@@ -430,8 +427,35 @@ static void ar934x_ip3_handler(void)
+@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
do_IRQ(ATH79_CPU_IRQ(3));
}
patches/openwrt/0019-base-files-default_postinst-propagate-the-real-postinst-return-code.patch deleted 100644 → 0
+ 0
− 44
View file @ 289b5992
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Fri, 7 Aug 2015 18:45:42 +0200
Subject: base-files: default_postinst: propagate the real postinst return code
Using the postinst script for sanity checks and expecting opkg to fail
if the postinst didn't return 0 was possible in Barrier Breaker, propagate
the real postinst return code through default_postinst to restore this
behaviour.
diff --git a/package/base-files/files/lib/functions.sh b/package/base-files/files/lib/functions.sh
index 8d045fa..2f78d67 100755
--- a/package/base-files/files/lib/functions.sh
+++ b/package/base-files/files/lib/functions.sh
@@ -174,7 +174,8 @@ default_prerm() {
}
default_postinst() {
- local pkgname rusers
+ local pkgname rusers ret
+ ret=0
pkgname=$(basename ${1%.*})
rusers=$(grep "Require-User:" ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.control)
[ -n "$rusers" ] && {
@@ -215,7 +216,10 @@ default_postinst() {
done
}
- [ -f ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.postinst-pkg ] && ( . ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.postinst-pkg )
+ if [ -f ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.postinst-pkg ]; then
+ ( . ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.postinst-pkg )
+ ret=$?
+ fi
[ -n "${IPKG_INSTROOT}" ] || rm -f /tmp/luci-indexcache 2>/dev/null
[ "$PKG_UPGRADE" = "1" ] || for i in `cat ${IPKG_INSTROOT}/usr/lib/opkg/info/${pkgname}.list | grep "^/etc/init.d/"`; do
@@ -225,7 +229,7 @@ default_postinst() {
$i start
}
done
- return 0
+ return $ret
}
include() {
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