diff --git a/include/profiles.mk b/include/profiles.mk
index a8a1700f25bdb370d3393dd3a66e8bf8e9865bbd..cb15c30c547b2ddf85e276f65074b1bda790ff0f 100644
--- a/include/profiles.mk
+++ b/include/profiles.mk
@@ -14,12 +14,13 @@ $(eval $(call GluonModel,TLWR741,tl-wr741nd-v1-squashfs,tp-link-tl-wr741n-nd-v1)
$(eval $(call GluonModel,TLWR741,tl-wr741nd-v2-squashfs,tp-link-tl-wr741n-nd-v2))
$(eval $(call GluonModel,TLWR741,tl-wr741nd-v4-squashfs,tp-link-tl-wr741n-nd-v4))
-# TL-WR841N/ND v3, v5, v7, v8
+# TL-WR841N/ND v3, v5, v7, v8, v9
$(eval $(call GluonProfile,TLWR841))
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v3-squashfs,tp-link-tl-wr841n-nd-v3))
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v5-squashfs,tp-link-tl-wr841n-nd-v5))
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v7-squashfs,tp-link-tl-wr841n-nd-v7))
$(eval $(call GluonModel,TLWR841,tl-wr841n-v8-squashfs,tp-link-tl-wr841n-nd-v8))
+$(eval $(call GluonModel,TLWR841,tl-wr841n-v9-squashfs,tp-link-tl-wr841n-nd-v9))
# TL-WR842N/ND v1
$(eval $(call GluonProfile,TLWR842))
diff --git a/kernel/config-ar71xx-generic b/kernel/config-ar71xx-generic
index 5a1e19cddb21021bca6f62d4dab42548488051b9..8cc5a0916546a9cab944408ad0d9659ea981aea6 100644
--- a/kernel/config-ar71xx-generic
+++ b/kernel/config-ar71xx-generic
@@ -112,6 +112,7 @@ CONFIG_ATH79_MACH_TL_WR741ND=y
CONFIG_ATH79_MACH_TL_WR741ND_V4=y
CONFIG_ATH79_MACH_TL_WR841N_V1=y
CONFIG_ATH79_MACH_TL_WR841N_V8=y
+CONFIG_ATH79_MACH_TL_WR841N_V9=y
CONFIG_ATH79_MACH_TL_WR941ND=y
CONFIG_ATH79_MACH_TL_WR1041N_V2=y
CONFIG_ATH79_MACH_TL_WR1043ND=y
@@ -128,6 +129,7 @@ CONFIG_SOC_AR724X=y
CONFIG_SOC_AR913X=y
CONFIG_SOC_AR933X=y
CONFIG_SOC_AR934X=y
+CONFIG_SOC_QCA953X=y
CONFIG_SOC_QCA955X=y
CONFIG_ATH79_DEV_AP9X_PCI=y
CONFIG_ATH79_DEV_DSA=y
diff --git a/patches/openwrt/0018-ar71xx-add-support-for-QCA953x-SoC.patch b/patches/openwrt/0018-ar71xx-add-support-for-QCA953x-SoC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6e2afc71ed805fe1308a338a09d3825958ec7678
--- /dev/null
+++ b/patches/openwrt/0018-ar71xx-add-support-for-QCA953x-SoC.patch
@@ -0,0 +1,713 @@
+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Sat, 29 Mar 2014 21:55:41 +0100
+Subject: ar71xx: add support for QCA953x SoC
+
+diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3
+index dfc5bf2..1c3ba3c 100644
+--- a/target/linux/ar71xx/config-3.3
++++ b/target/linux/ar71xx/config-3.3
+@@ -40,11 +40,11 @@ CONFIG_ATH79_MACH_EW_DORIN=y
+ CONFIG_ATH79_MACH_HORNET_UB=y
+ CONFIG_ATH79_MACH_JA76PF=y
+ CONFIG_ATH79_MACH_JWAP003=y
++CONFIG_ATH79_MACH_MR600=y
+ CONFIG_ATH79_MACH_MZK_W04NU=y
+ CONFIG_ATH79_MACH_MZK_W300NH=y
+ CONFIG_ATH79_MACH_NBG460N=y
+ CONFIG_ATH79_MACH_OM2P=y
+-CONFIG_ATH79_MACH_MR600=y
+ CONFIG_ATH79_MACH_PB42=y
+ CONFIG_ATH79_MACH_PB44=y
+ CONFIG_ATH79_MACH_PB92=y
+@@ -214,6 +214,7 @@ CONFIG_SOC_AR724X=y
+ CONFIG_SOC_AR913X=y
+ CONFIG_SOC_AR933X=y
+ CONFIG_SOC_AR934X=y
++CONFIG_SOC_QCA953X=y
+ CONFIG_SOC_QCA955X=y
+ CONFIG_SPI=y
+ CONFIG_SPI_AP83=y
+diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+index 5a0b950..1a9b0df 100644
+--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
++++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+@@ -195,6 +195,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
++ case ATH79_SOC_QCA9533:
+ mdio_dev = &ath79_mdio1_device;
+ mdio_data = &ath79_mdio1_data;
+ break;
+@@ -250,6 +251,11 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
+ }
+ mdio_data->is_ar934x = 1;
+ break;
++
++ case ATH79_SOC_QCA9533:
++ mdio_data->builtin_switch = 1;
++ break;
++
+ case ATH79_SOC_QCA9558:
+ if (id == 1)
+ mdio_data->builtin_switch = 1;
+@@ -540,6 +546,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
++ case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9558:
+ pll_10 = AR934X_PLL_VAL_10;
+ pll_100 = AR934X_PLL_VAL_100;
+@@ -596,6 +603,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
++ case ATH79_SOC_QCA9533:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
+ break;
+
+@@ -645,6 +653,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
++ case ATH79_SOC_QCA9533:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
+ break;
+
+@@ -882,6 +891,37 @@ void __init ath79_register_eth(unsigned int id)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
++ case ATH79_SOC_QCA9533:
++ if (id == 0) {
++ pdata->reset_bit = AR933X_RESET_GE0_MAC |
++ AR933X_RESET_GE0_MDIO;
++ pdata->set_speed = ath79_set_speed_dummy;
++
++ pdata->phy_mask = BIT(4);
++ } else {
++ pdata->reset_bit = AR933X_RESET_GE1_MAC |
++ AR933X_RESET_GE1_MDIO;
++ pdata->set_speed = ath79_set_speed_dummy;
++
++ pdata->speed = SPEED_1000;
++ pdata->duplex = DUPLEX_FULL;
++ pdata->switch_data = &ath79_switch_data;
++
++ ath79_switch_data.phy_poll_mask |= BIT(4);
++ }
++
++ pdata->ddr_flush = ath79_ddr_no_flush;
++ pdata->has_gbit = 1;
++ pdata->is_ar724x = 1;
++
++ if (!pdata->fifo_cfg1)
++ pdata->fifo_cfg1 = 0x0010ffff;
++ if (!pdata->fifo_cfg2)
++ pdata->fifo_cfg2 = 0x015500aa;
++ if (!pdata->fifo_cfg3)
++ pdata->fifo_cfg3 = 0x01f00140;
++ break;
++
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+@@ -953,6 +993,7 @@ void __init ath79_register_eth(unsigned int id)
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
++ case ATH79_SOC_QCA9533:
+ pdata->mii_bus_dev = &ath79_mdio1_device.dev;
+ break;
+
+diff --git a/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+new file mode 100644
+index 0000000..bd08685
+--- /dev/null
++++ b/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+@@ -0,0 +1,584 @@
++From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
++Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
++From: Matthias Schiffer <mschiffer@universe-factory.net>
++Date: Sat, 29 Mar 2014 20:26:08 +0100
++Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
++
++Note that the clock calculation looks very similar to the QCA955x, but actually
++some bits' meanings are slightly different.
++---
++ arch/mips/ath79/Kconfig | 6 +-
++ arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
++ arch/mips/ath79/common.c | 4 ++
++ arch/mips/ath79/dev-common.c | 1 +
++ arch/mips/ath79/dev-wmac.c | 20 +++++++
++ arch/mips/ath79/early_printk.c | 1 +
++ arch/mips/ath79/gpio.c | 4 +-
++ arch/mips/ath79/irq.c | 4 ++
++ arch/mips/ath79/setup.c | 8 ++-
++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
++ arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
++ 11 files changed, 182 insertions(+), 3 deletions(-)
++
++--- a/arch/mips/ath79/Kconfig
+++++ b/arch/mips/ath79/Kconfig
++@@ -698,6 +698,10 @@ config SOC_AR934X
++ select PCI_AR724X if PCI
++ def_bool n
++
+++config SOC_QCA953X
+++ select USB_ARCH_HAS_EHCI
+++ def_bool n
+++
++ config SOC_QCA955X
++ select USB_ARCH_HAS_EHCI
++ select HW_HAS_PCI
++@@ -741,7 +745,7 @@ config ATH79_DEV_USB
++ def_bool n
++
++ config ATH79_DEV_WMAC
++- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
++ def_bool n
++
++ config ATH79_NVRAM
++--- a/arch/mips/ath79/clock.c
+++++ b/arch/mips/ath79/clock.c
++@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
++ iounmap(dpll_base);
++ }
++
+++static void __init qca953x_clocks_init(void)
+++{
+++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
+++ u32 cpu_pll, ddr_pll;
+++ u32 bootstrap;
+++
+++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
+++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
+++ ath79_ref_clk.rate = 40 * 1000 * 1000;
+++ else
+++ ath79_ref_clk.rate = 25 * 1000 * 1000;
+++
+++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
+++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
+++ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
+++
+++ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
+++ cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
+++ cpu_pll /= (1 << out_div);
+++
+++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
+++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
+++ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
+++
+++ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
+++ ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
+++ ddr_pll /= (1 << out_div);
+++
+++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
+++
+++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+++
+++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+++ ath79_cpu_clk.rate = ath79_ref_clk.rate;
+++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
+++ else
+++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
+++
+++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+++
+++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+++ ath79_ddr_clk.rate = ath79_ref_clk.rate;
+++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
+++ else
+++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
+++
+++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+++
+++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+++ ath79_ahb_clk.rate = ath79_ref_clk.rate;
+++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
+++ else
+++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
+++
+++ ath79_wdt_clk.rate = ath79_ref_clk.rate;
+++ ath79_uart_clk.rate = ath79_ref_clk.rate;
+++}
+++
++ static void __init qca955x_clocks_init(void)
++ {
++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++@@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
++ ar933x_clocks_init();
++ else if (soc_is_ar934x())
++ ar934x_clocks_init();
+++ else if (soc_is_qca953x())
+++ qca953x_clocks_init();
++ else if (soc_is_qca955x())
++ qca955x_clocks_init();
++ else
++--- a/arch/mips/ath79/common.c
+++++ b/arch/mips/ath79/common.c
++@@ -71,9 +71,12 @@ void ath79_device_reset_set(u32 mask)
++ reg = AR913X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar933x())
++ reg = AR933X_RESET_REG_RESET_MODULE;
++- else if (soc_is_ar934x() ||
++- soc_is_qca955x())
+++ else if (soc_is_ar934x())
++ reg = AR934X_RESET_REG_RESET_MODULE;
+++ else if (soc_is_qca953x())
+++ reg = QCA953X_RESET_REG_RESET_MODULE;
+++ else if (soc_is_qca955x())
+++ reg = QCA955X_RESET_REG_RESET_MODULE;
++ else
++ BUG();
++
++@@ -98,9 +101,12 @@ void ath79_device_reset_clear(u32 mask)
++ reg = AR913X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar933x())
++ reg = AR933X_RESET_REG_RESET_MODULE;
++- else if (soc_is_ar934x() ||
++- soc_is_qca955x())
+++ else if (soc_is_ar934x())
++ reg = AR934X_RESET_REG_RESET_MODULE;
+++ else if (soc_is_qca953x())
+++ reg = QCA953X_RESET_REG_RESET_MODULE;
+++ else if (soc_is_qca955x())
+++ reg = QCA955X_RESET_REG_RESET_MODULE;
++ else
++ BUG();
++
++--- a/arch/mips/ath79/dev-common.c
+++++ b/arch/mips/ath79/dev-common.c
++@@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
++ soc_is_ar724x() ||
++ soc_is_ar913x() ||
++ soc_is_ar934x() ||
+++ soc_is_qca953x() ||
++ soc_is_qca955x()) {
++ ath79_uart_data[0].uartclk = clk_get_rate(clk);
++ platform_device_register(&ath79_uart_device);
++--- a/arch/mips/ath79/dev-wmac.c
+++++ b/arch/mips/ath79/dev-wmac.c
++@@ -147,6 +147,24 @@ static void ar934x_wmac_setup(void)
++ ath79_wmac_data.is_clk_25mhz = true;
++ }
++
+++static void qca953x_wmac_setup(void)
+++{
+++ u32 t;
+++
+++ ath79_wmac_device.name = "qca953x_wmac";
+++
+++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
+++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
+++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
+++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
+++
+++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
+++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
+++ ath79_wmac_data.is_clk_25mhz = false;
+++ else
+++ ath79_wmac_data.is_clk_25mhz = true;
+++}
+++
++ static void qca955x_wmac_setup(void)
++ {
++ u32 t;
++@@ -314,6 +332,8 @@ void __init ath79_register_wmac(u8 *cal_
++ ar933x_wmac_setup();
++ else if (soc_is_ar934x())
++ ar934x_wmac_setup();
+++ else if (soc_is_qca953x())
+++ qca953x_wmac_setup();
++ else if (soc_is_qca955x())
++ qca955x_wmac_setup();
++ else
++--- a/arch/mips/ath79/early_printk.c
+++++ b/arch/mips/ath79/early_printk.c
++@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
++ case REV_ID_MAJOR_AR9341:
++ case REV_ID_MAJOR_AR9342:
++ case REV_ID_MAJOR_AR9344:
+++ case REV_ID_MAJOR_QCA9533:
++ case REV_ID_MAJOR_QCA9558:
++ _prom_putchar = prom_putchar_ar71xx;
++ break;
++--- a/arch/mips/ath79/gpio.c
+++++ b/arch/mips/ath79/gpio.c
++@@ -232,14 +232,18 @@ void __init ath79_gpio_init(void)
++
++ if (soc_is_ar71xx())
++ ath79_gpio_count = AR71XX_GPIO_COUNT;
++- else if (soc_is_ar724x())
++- ath79_gpio_count = AR724X_GPIO_COUNT;
+++ else if (soc_is_ar7240())
+++ ath79_gpio_count = AR7240_GPIO_COUNT;
+++ else if (soc_is_ar7241() || soc_is_ar7242())
+++ ath79_gpio_count = AR7241_GPIO_COUNT;
++ else if (soc_is_ar913x())
++ ath79_gpio_count = AR913X_GPIO_COUNT;
++ else if (soc_is_ar933x())
++ ath79_gpio_count = AR933X_GPIO_COUNT;
++ else if (soc_is_ar934x())
++ ath79_gpio_count = AR934X_GPIO_COUNT;
+++ else if (soc_is_qca953x())
+++ ath79_gpio_count = QCA953X_GPIO_COUNT;
++ else if (soc_is_qca955x())
++ ath79_gpio_count = QCA955X_GPIO_COUNT;
++ else
++@@ -247,7 +251,7 @@ void __init ath79_gpio_init(void)
++
++ ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
++ ath79_gpio_chip.ngpio = ath79_gpio_count;
++- if (soc_is_ar934x() || soc_is_qca955x()) {
+++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
++ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
++ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
++ }
++--- a/arch/mips/ath79/irq.c
+++++ b/arch/mips/ath79/irq.c
++@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
++ else if (soc_is_ar724x() ||
++ soc_is_ar933x() ||
++ soc_is_ar934x() ||
+++ soc_is_qca953x() ||
++ soc_is_qca955x())
++ ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
++ else
++@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
++ } else if (soc_is_ar934x()) {
++ ath79_ip2_handler = ath79_default_ip2_handler;
++ ath79_ip3_handler = ar934x_ip3_handler;
+++ } else if (soc_is_qca953x()) {
+++ ath79_ip2_handler = ath79_default_ip2_handler;
+++ ath79_ip3_handler = ath79_default_ip3_handler;
++ } else if (soc_is_qca955x()) {
++ ath79_ip2_handler = ath79_default_ip2_handler;
++ ath79_ip3_handler = ath79_default_ip3_handler;
++--- a/arch/mips/ath79/setup.c
+++++ b/arch/mips/ath79/setup.c
++@@ -164,10 +164,16 @@ static void __init ath79_detect_sys_type
++ rev = id & AR934X_REV_ID_REVISION_MASK;
++ break;
++
+++ case REV_ID_MAJOR_QCA9533:
+++ ath79_soc = ATH79_SOC_QCA9533;
+++ chip = "9533";
+++ rev = id & QCA955X_REV_ID_REVISION_MASK;
+++ break;
+++
++ case REV_ID_MAJOR_QCA9558:
++ ath79_soc = ATH79_SOC_QCA9558;
++ chip = "9558";
++- rev = id & AR944X_REV_ID_REVISION_MASK;
+++ rev = id & QCA955X_REV_ID_REVISION_MASK;
++ break;
++
++ default:
++@@ -176,7 +182,7 @@ static void __init ath79_detect_sys_type
++
++ ath79_soc_rev = rev;
++
++- if (soc_is_qca955x())
+++ if (soc_is_qca953x() || soc_is_qca955x())
++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++ chip, rev);
++ else
++--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++@@ -38,8 +38,8 @@
++ #define AR71XX_UART_SIZE 0x100
++ #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
++ #define AR71XX_USB_CTRL_SIZE 0x100
++-#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
++-#define AR71XX_GPIO_SIZE 0x100
+++#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
+++#define AR71XX_GPIO_SIZE 0x100
++ #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
++ #define AR71XX_PLL_SIZE 0x100
++ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
++@@ -101,10 +101,13 @@
++ #define AR934X_WMAC_SIZE 0x20000
++ #define AR934X_EHCI_BASE 0x1b000000
++ #define AR934X_EHCI_SIZE 0x200
++-#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
++-#define AR934X_SRIF_SIZE 0x1000
++ #define AR934X_NFC_BASE 0x1b000200
++ #define AR934X_NFC_SIZE 0xb8
+++#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+++#define AR934X_SRIF_SIZE 0x1000
+++
+++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+++#define QCA953X_WMAC_SIZE 0x20000
++
++ #define QCA955X_PCI_MEM_BASE0 0x10000000
++ #define QCA955X_PCI_MEM_BASE1 0x12000000
++@@ -119,14 +122,14 @@
++ #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
++ #define QCA955X_PCI_CTRL_SIZE 0x100
++
+++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+++#define QCA955X_GMAC_SIZE 0x40
++ #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
++ #define QCA955X_WMAC_SIZE 0x20000
++ #define QCA955X_EHCI0_BASE 0x1b000000
++ #define QCA955X_EHCI1_BASE 0x1b400000
++-#define QCA955X_EHCI_SIZE 0x200
++-#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
++-#define QCA955X_GMAC_SIZE 0x40
++-#define QCA955X_NFC_BASE 0x1b000200
+++#define QCA955X_EHCI_SIZE 0x1000
+++#define QCA955X_NFC_BASE 0x1b800200
++ #define QCA955X_NFC_SIZE 0xb8
++
++ #define AR9300_OTP_BASE 0x14000
++@@ -280,9 +283,48 @@
++
++ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
++
+++#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+++#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+++#define QCA953X_PLL_CLK_CTRL_REG 0x08
+++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
+++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
+++
+++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
+++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+++
+++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
+++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+++
+++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+++
++ #define QCA955X_PLL_CPU_CONFIG_REG 0x00
++ #define QCA955X_PLL_DDR_CONFIG_REG 0x04
++ #define QCA955X_PLL_CLK_CTRL_REG 0x08
+++#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
+++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
++
++ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
++ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
++@@ -354,6 +396,11 @@
++ #define AR934X_RESET_REG_BOOTSTRAP 0xb0
++ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
++
+++#define QCA953X_RESET_REG_RESET_MODULE 0x1c
+++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
+++#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac
+++
+++#define QCA955X_RESET_REG_RESET_MODULE 0x1c
++ #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
++ #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
++
++@@ -448,6 +495,39 @@
++ #define AR934X_RESET_MBOX BIT(1)
++ #define AR934X_RESET_I2S BIT(0)
++
+++#define QCA955X_RESET_HOST BIT(31)
+++#define QCA955X_RESET_SLIC BIT(30)
+++#define QCA955X_RESET_HDMA BIT(29)
+++#define QCA955X_RESET_EXTERNAL BIT(28)
+++#define QCA955X_RESET_RTC BIT(27)
+++#define QCA955X_RESET_PCIE_EP_INT BIT(26)
+++#define QCA955X_RESET_CHKSUM_ACC BIT(25)
+++#define QCA955X_RESET_FULL_CHIP BIT(24)
+++#define QCA955X_RESET_GE1_MDIO BIT(23)
+++#define QCA955X_RESET_GE0_MDIO BIT(22)
+++#define QCA955X_RESET_CPU_NMI BIT(21)
+++#define QCA955X_RESET_CPU_COLD BIT(20)
+++#define QCA955X_RESET_HOST_RESET_INT BIT(19)
+++#define QCA955X_RESET_PCIE_EP BIT(18)
+++#define QCA955X_RESET_UART1 BIT(17)
+++#define QCA955X_RESET_DDR BIT(16)
+++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+++#define QCA955X_RESET_NANDF BIT(14)
+++#define QCA955X_RESET_GE1_MAC BIT(13)
+++#define QCA955X_RESET_SGMII_ANALOG BIT(12)
+++#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
+++#define QCA955X_RESET_HOST_DMA_INT BIT(10)
+++#define QCA955X_RESET_GE0_MAC BIT(9)
+++#define QCA955X_RESET_SGMII BIT(8)
+++#define QCA955X_RESET_PCIE_PHY BIT(7)
+++#define QCA955X_RESET_PCIE BIT(6)
+++#define QCA955X_RESET_USB_HOST BIT(5)
+++#define QCA955X_RESET_USB_PHY BIT(4)
+++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
+++#define QCA955X_RESET_LUT BIT(2)
+++#define QCA955X_RESET_MBOX BIT(1)
+++#define QCA955X_RESET_I2S BIT(0)
+++
++ #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
++ #define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
++ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
++@@ -465,9 +545,11 @@
++ #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
++ #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
++ #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
++-#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++ #define AR934X_BOOTSTRAP_DDR1 BIT(0)
++
+++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
+++
++ #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
++
++ #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
++@@ -530,6 +612,8 @@
++ #define REV_ID_MAJOR_AR9341 0x0120
++ #define REV_ID_MAJOR_AR9342 0x1120
++ #define REV_ID_MAJOR_AR9344 0x2120
+++#define REV_ID_MAJOR_QCA9533 0x0140
+++#define REV_ID_MAJOR_QCA9556 0x0130
++ #define REV_ID_MAJOR_QCA9558 0x1130
++
++ #define AR71XX_REV_ID_MINOR_MASK 0x3
++@@ -549,9 +633,9 @@
++
++ #define AR724X_REV_ID_REVISION_MASK 0x3
++
++-#define AR934X_REV_ID_REVISION_MASK 0xf
+++#define AR934X_REV_ID_REVISION_MASK 0xf
++
++-#define AR944X_REV_ID_REVISION_MASK 0xf
+++#define QCA955X_REV_ID_REVISION_MASK 0xf
++
++ /*
++ * SPI block
++@@ -599,10 +683,12 @@
++ #define AR934X_GPIO_REG_FUNC 0x6c
++
++ #define AR71XX_GPIO_COUNT 16
++-#define AR724X_GPIO_COUNT 18
+++#define AR7240_GPIO_COUNT 18
+++#define AR7241_GPIO_COUNT 20
++ #define AR913X_GPIO_COUNT 22
++ #define AR933X_GPIO_COUNT 30
++ #define AR934X_GPIO_COUNT 23
+++#define QCA953X_GPIO_COUNT 24 /* (?) */
++ #define QCA955X_GPIO_COUNT 24
++
++ /*
++@@ -693,12 +779,14 @@
++ #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
++ #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
++
++-#define AR934X_GPIO_OUT_GPIO 0
++-#define AR934X_GPIO_OUT_LED_LINK0 41
++-#define AR934X_GPIO_OUT_LED_LINK1 42
++-#define AR934X_GPIO_OUT_LED_LINK2 43
++-#define AR934X_GPIO_OUT_LED_LINK3 44
++-#define AR934X_GPIO_OUT_LED_LINK4 45
+++#define AR934X_GPIO_OUT_GPIO 0
+++#define AR934X_GPIO_OUT_LED_LINK0 41
+++#define AR934X_GPIO_OUT_LED_LINK1 42
+++#define AR934X_GPIO_OUT_LED_LINK2 43
+++#define AR934X_GPIO_OUT_LED_LINK3 44
+++#define AR934X_GPIO_OUT_LED_LINK4 45
+++#define AR934X_GPIO_OUT_EXT_LNA0 46
+++#define AR934X_GPIO_OUT_EXT_LNA1 47
++
++ /*
++ * MII_CTRL block
++@@ -756,6 +844,8 @@
++ #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
++ #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
++ #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+++#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
+++#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
++
++ /*
++ * QCA955X GMAC Interface
++@@ -763,7 +853,7 @@
++
++ #define QCA955X_GMAC_REG_ETH_CFG 0x00
++
++-#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0)
++-#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6)
+++#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+++#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
++
++ #endif /* __ASM_MACH_AR71XX_REGS_H */
++--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++++ b/arch/mips/include/asm/mach-ath79/ath79.h
++@@ -32,6 +32,7 @@ enum ath79_soc_type {
++ ATH79_SOC_AR9341,
++ ATH79_SOC_AR9342,
++ ATH79_SOC_AR9344,
+++ ATH79_SOC_QCA9533,
++ ATH79_SOC_QCA9558,
++ };
++
++@@ -99,6 +100,16 @@ static inline int soc_is_ar934x(void)
++ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
++ }
++
+++static inline int soc_is_qca9533(void)
+++{
+++ return ath79_soc == ATH79_SOC_QCA9533;
+++}
+++
+++static inline int soc_is_qca953x(void)
+++{
+++ return soc_is_qca9533();
+++}
+++
++ static inline int soc_is_qca9558(void)
++ {
++ return ath79_soc == ATH79_SOC_QCA9558;
++--- a/arch/mips/ath79/mach-ap136.c
+++++ b/arch/mips/ath79/mach-ap136.c
++@@ -149,8 +149,8 @@ static void __init ap136_gmac_setup(void
++
++ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++- t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
++- t |= QCA955X_ETH_CFG_RGMII_GMAC0;
+++ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+++ t |= QCA955X_ETH_CFG_RGMII_EN;
++
++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
++
diff --git a/patches/openwrt/0019-ar71xx-add-support-for-the-TP-LINK-TL-WR841N-ND-v9.patch b/patches/openwrt/0019-ar71xx-add-support-for-the-TP-LINK-TL-WR841N-ND-v9.patch
new file mode 100644
index 0000000000000000000000000000000000000000..201d629e07212e5cf9d996efe6fb96d78dadcaab
--- /dev/null
+++ b/patches/openwrt/0019-ar71xx-add-support-for-the-TP-LINK-TL-WR841N-ND-v9.patch
@@ -0,0 +1,297 @@
+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Sat, 29 Mar 2014 21:12:15 +0100
+Subject: ar71xx: add support for the TP-LINK TL-WR841N/ND v9
+
+diff --git a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh
+index b206438..0bf2dd1 100755
+--- a/target/linux/ar71xx/base-files/etc/diag.sh
++++ b/target/linux/ar71xx/base-files/etc/diag.sh
+@@ -144,6 +144,9 @@ get_status_led() {
+ tl-wr703n)
+ status_led="tp-link:blue:system"
+ ;;
++ tl-wr841n-v9)
++ status_led="tp-link:green:qss"
++ ;;
+ tl-wr2543n)
+ status_led="tp-link:green:wps"
+ ;;
+diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/leds b/target/linux/ar71xx/base-files/etc/uci-defaults/leds
+index 48b8154..43bc24d 100755
+--- a/target/linux/ar71xx/base-files/etc/uci-defaults/leds
++++ b/target/linux/ar71xx/base-files/etc/uci-defaults/leds
+@@ -163,6 +163,15 @@ tl-wr841n-v8)
+ ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt"
+ ;;
+
++tl-wr841n-v9)
++ ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1"
++ ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10"
++ ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08"
++ ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x04"
++ ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02"
++ ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt"
++ ;;
++
+ tl-wr941nd | \
+ tl-wr1041n-v2)
+ ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt"
+diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/network b/target/linux/ar71xx/base-files/etc/uci-defaults/network
+index a36036f..a1dfda0 100755
+--- a/target/linux/ar71xx/base-files/etc/uci-defaults/network
++++ b/target/linux/ar71xx/base-files/etc/uci-defaults/network
+@@ -192,6 +192,7 @@ tl-wdr3500 |\
+ tl-wr741nd |\
+ tl-wr741nd-v4 |\
+ tl-wr841n-v7 |\
++tl-wr841n-v9 |\
+ whr-g301n |\
+ whr-hp-g300n |\
+ whr-hp-gn |\
+diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh
+index 8d71352..ca174da 100755
+--- a/target/linux/ar71xx/base-files/lib/ar71xx.sh
++++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh
+@@ -381,6 +381,9 @@ ar71xx_board_detect() {
+ *"TL-WR841N/ND v8")
+ name="tl-wr841n-v8"
+ ;;
++ *"TL-WR841N/ND v9")
++ name="tl-wr841n-v9"
++ ;;
+ *TL-WR941ND)
+ name="tl-wr941nd"
+ ;;
+diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
+index e52ad9e..7168b4e 100755
+--- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
++++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
+@@ -163,6 +163,7 @@ platform_check_image() {
+ tl-wr841n-v1 | \
+ tl-wr841n-v7 | \
+ tl-wr841n-v8 | \
++ tl-wr841n-v9 | \
+ tl-wr941nd | \
+ tl-wr1041n-v2 | \
+ tl-wr1043nd | \
+diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3
+index 1c3ba3c..82d4d21 100644
+--- a/target/linux/ar71xx/config-3.3
++++ b/target/linux/ar71xx/config-3.3
+@@ -70,6 +70,7 @@ CONFIG_ATH79_MACH_TL_WR741ND=y
+ CONFIG_ATH79_MACH_TL_WR741ND_V4=y
+ CONFIG_ATH79_MACH_TL_WR841N_V1=y
+ CONFIG_ATH79_MACH_TL_WR841N_V8=y
++CONFIG_ATH79_MACH_TL_WR841N_V9=y
+ CONFIG_ATH79_MACH_TL_WR941ND=y
+ CONFIG_ATH79_MACH_UBNT=y
+ CONFIG_ATH79_MACH_UBNT_XM=y
+diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
+new file mode 100644
+index 0000000..c28afc6
+--- /dev/null
++++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
+@@ -0,0 +1,138 @@
++/*
++ * TP-LINK TL-WR841N/ND v9
++ *
++ * Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-eth.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
++#include "dev-wmac.h"
++#include "machtypes.h"
++
++#define TL_WR841NV9_GPIO_LED_WLAN 13
++#define TL_WR841NV9_GPIO_LED_QSS 3
++#define TL_WR841NV9_GPIO_LED_WAN 4
++#define TL_WR841NV9_GPIO_LED_LAN1 16
++#define TL_WR841NV9_GPIO_LED_LAN2 15
++#define TL_WR841NV9_GPIO_LED_LAN3 14
++#define TL_WR841NV9_GPIO_LED_LAN4 11
++
++#define TL_WR841NV9_GPIO_BTN_RESET 12
++#define TL_WR841NV9_GPIO_BTN_WIFI 17
++
++#define TL_WR841NV9_KEYS_POLL_INTERVAL 20 /* msecs */
++#define TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV9_KEYS_POLL_INTERVAL)
++
++static const char *tl_wr841n_v9_part_probes[] = {
++ "tp-link",
++ NULL,
++};
++
++static struct flash_platform_data tl_wr841n_v9_flash_data = {
++ .part_probes = tl_wr841n_v9_part_probes,
++};
++
++static struct gpio_led tl_wr841n_v9_leds_gpio[] __initdata = {
++ {
++ .name = "tp-link:green:lan1",
++ .gpio = TL_WR841NV9_GPIO_LED_LAN1,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:lan2",
++ .gpio = TL_WR841NV9_GPIO_LED_LAN2,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:lan3",
++ .gpio = TL_WR841NV9_GPIO_LED_LAN3,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:lan4",
++ .gpio = TL_WR841NV9_GPIO_LED_LAN4,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:qss",
++ .gpio = TL_WR841NV9_GPIO_LED_QSS,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:wan",
++ .gpio = TL_WR841NV9_GPIO_LED_WAN,
++ .active_low = 1,
++ }, {
++ .name = "tp-link:green:wlan",
++ .gpio = TL_WR841NV9_GPIO_LED_WLAN,
++ .active_low = 1,
++ },
++};
++
++static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = {
++ {
++ .desc = "Reset button",
++ .type = EV_KEY,
++ .code = KEY_RESTART,
++ .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = TL_WR841NV9_GPIO_BTN_RESET,
++ .active_low = 1,
++ }, {
++ .desc = "WIFI button",
++ .type = EV_KEY,
++ .code = KEY_RFKILL,
++ .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = TL_WR841NV9_GPIO_BTN_WIFI,
++ .active_low = 1,
++ }
++};
++
++
++static void __init tl_ap143_setup(void)
++{
++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++ u8 tmpmac[ETH_ALEN];
++
++ ath79_register_m25p80(&tl_wr841n_v9_flash_data);
++
++ ath79_setup_ar933x_phy4_switch(false, false);
++
++ ath79_register_mdio(0, 0x0);
++
++ /* LAN */
++ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
++ ath79_register_eth(1);
++
++ /* WAN */
++ ath79_switch_data.phy4_mii_en = 1;
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
++ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
++ ath79_register_eth(0);
++
++ ath79_init_mac(tmpmac, mac, 0);
++ ath79_register_wmac(ee, tmpmac);
++}
++
++static void __init tl_wr841n_v9_setup(void)
++{
++ tl_ap143_setup();
++
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v9_leds_gpio),
++ tl_wr841n_v9_leds_gpio);
++
++ ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(tl_wr841n_v9_gpio_keys),
++ tl_wr841n_v9_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9",
++ tl_wr841n_v9_setup);
+diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile
+index 01d1e67..c270f73 100644
+--- a/target/linux/ar71xx/image/Makefile
++++ b/target/linux/ar71xx/image/Makefile
+@@ -879,6 +879,7 @@ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR703,tl-wr703n-v1,TL-WR7
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR740NV4,tl-wr740n-v4,TL-WR741ND-v4,ttyATH0,115200,0x07400004,1,4Mlzma))
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR741NV4,tl-wr741nd-v4,TL-WR741ND-v4,ttyATH0,115200,0x07410004,1,4Mlzma))
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR841NV8,tl-wr841n-v8,TL-WR841N-v8,ttyS0,115200,0x08410008,1,4Mlzma))
++$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR841NV9,tl-wr841n-v9,TL-WR841N-v9,ttyS0,115200,0x08410009,1,4Mlzma))
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR1041,tl-wr1041n-v2,TL-WR1041N-v2,ttyS0,115200,0x10410002,1,4Mlzma))
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR2543,tl-wr2543-v1,TL-WR2543N,ttyS0,115200,0x25430001,1,8Mlzma,-v 3.13.99))
+ $(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWDR3500V1,tl-wdr3500-v1,TL-WDR3500,ttyS0,115200,0x35000001,1,8Mlzma))
+@@ -924,7 +925,7 @@ $(eval $(call MultiProfile,TLWA901,TLWA901NV1 TLWA901NV2))
+ $(eval $(call MultiProfile,TLWA7510,TLWA7510NV1))
+ $(eval $(call MultiProfile,TLWR740,TLWR740NV1 TLWR740NV3 TLWR740NV4))
+ $(eval $(call MultiProfile,TLWR741,TLWR741NV1 TLWR741NV2 TLWR741NV4))
+-$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7 TLWR841NV8))
++$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7 TLWR841NV8 TLWR841NV9))
+ $(eval $(call MultiProfile,TLWR941,TLWR941NV2 TLWR941NV3 TLWR941NV4))
+ $(eval $(call MultiProfile,TLWDR4300,TLWDR3500V1 TLWDR3600V1 TLWDR4300V1 TLWDR4310V1))
+ $(eval $(call MultiProfile,UBNT,UBNTAIRROUTER UBNTRS UBNTRSPRO UBNTLSSR71 UBNTBULLETM UBNTROCKETM UBNTNANOM UBNTUNIFI UBNTUNIFIOUTDOOR))
+diff --git a/target/linux/ar71xx/patches-3.3/706-MIPS-ath79-TL-WR841v9-support.patch b/target/linux/ar71xx/patches-3.3/706-MIPS-ath79-TL-WR841v9-support.patch
+new file mode 100644
+index 0000000..ebc82c6
+--- /dev/null
++++ b/target/linux/ar71xx/patches-3.3/706-MIPS-ath79-TL-WR841v9-support.patch
+@@ -0,0 +1,38 @@
++--- a/arch/mips/ath79/Kconfig
+++++ b/arch/mips/ath79/Kconfig
++@@ -547,6 +547,15 @@ config ATH79_MACH_TL_WR841N_V8
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
+++config ATH79_MACH_TL_WR841N_V9
+++ bool "TP-LINK TL-WR841N/ND v9 support"
+++ select SOC_QCA953X
+++ select ATH79_DEV_ETH
+++ select ATH79_DEV_GPIO_BUTTONS
+++ select ATH79_DEV_LEDS_GPIO
+++ select ATH79_DEV_M25P80
+++ select ATH79_DEV_WMAC
+++
++ config ATH79_MACH_TL_WR941ND
++ bool "TP-LINK TL-WR941ND support"
++ select SOC_AR913X
++--- a/arch/mips/ath79/Makefile
+++++ b/arch/mips/ath79/Makefile
++@@ -85,6 +85,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += m
++ obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
++ obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
++ obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o
+++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
++ obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
++ obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o
++ obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
++--- a/arch/mips/ath79/machtypes.h
+++++ b/arch/mips/ath79/machtypes.h
++@@ -91,6 +91,7 @@ enum ath79_mach_type {
++ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */
++ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
++ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */
+++ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */
++ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
++ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
++ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
diff --git a/patches/packages/mac80211/0001-mac80211-ath9k-add-support-for-QCA953x.patch b/patches/packages/mac80211/0001-mac80211-ath9k-add-support-for-QCA953x.patch
new file mode 100644
index 0000000000000000000000000000000000000000..c5965dd7b2f0cda47878746bd4ed3196dae82bdb
--- /dev/null
+++ b/patches/packages/mac80211/0001-mac80211-ath9k-add-support-for-QCA953x.patch
@@ -0,0 +1,140 @@
+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Sat, 29 Mar 2014 21:33:11 +0100
+Subject: mac80211: ath9k: add support for QCA953x
+
+This adds the following patches by Sujith Manoharan from ath9k-devel:
+
+ath9k: Add QCA953x WMAC platform support
+ath9k: Disable AR_INTR_SYNC_HOST1_FATAL for QCA953x
+ath9k: Fix temperature compensation
+
+diff --git a/mac80211/patches/567-ath9k-qca953x-support.patch b/mac80211/patches/567-ath9k-qca953x-support.patch
+new file mode 100644
+index 0000000..e73083a
+--- /dev/null
++++ b/mac80211/patches/567-ath9k-qca953x-support.patch
+@@ -0,0 +1,124 @@
++--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++++ b/drivers/net/wireless/ath/ath9k/ahb.c
++@@ -39,6 +39,10 @@ static const struct platform_device_id a
++ .name = "qca955x_wmac",
++ .driver_data = AR9300_DEVID_QCA955X,
++ },
+++ {
+++ .name = "qca953x_wmac",
+++ .driver_data = AR9300_DEVID_AR953X,
+++ },
++ {},
++ };
++
++--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++@@ -4792,43 +4792,54 @@ static void ar9003_hw_power_control_over
++
++ tempslope:
++ if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
+++ u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
+++
++ /*
++ * AR955x has tempSlope register for each chain.
++ * Check whether temp_compensation feature is enabled or not.
++ */
++ if (eep->baseEepHeader.featureEnable & 0x1) {
++ if (frequency < 4000) {
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- eep->base_ext2.tempSlopeLow);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- temp_slope);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- eep->base_ext2.tempSlopeHigh);
+++ if (txmask & BIT(0))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ eep->base_ext2.tempSlopeLow);
+++ if (txmask & BIT(1))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ temp_slope);
+++ if (txmask & BIT(2))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ eep->base_ext2.tempSlopeHigh);
++ } else {
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- temp_slope);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- temp_slope1);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
++- AR_PHY_TPC_19_ALPHA_THERM,
++- temp_slope2);
+++ if (txmask & BIT(0))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ temp_slope);
+++ if (txmask & BIT(1))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ temp_slope1);
+++ if (txmask & BIT(2))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
+++ AR_PHY_TPC_19_ALPHA_THERM,
+++ temp_slope2);
++ }
++ } else {
++ /*
++ * If temp compensation is not enabled,
++ * set all registers to 0.
++ */
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
++- AR_PHY_TPC_19_ALPHA_THERM, 0);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
++- AR_PHY_TPC_19_ALPHA_THERM, 0);
++- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
++- AR_PHY_TPC_19_ALPHA_THERM, 0);
+++ if (txmask & BIT(0))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
+++ AR_PHY_TPC_19_ALPHA_THERM, 0);
+++ if (txmask & BIT(1))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
+++ AR_PHY_TPC_19_ALPHA_THERM, 0);
+++ if (txmask & BIT(2))
+++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
+++ AR_PHY_TPC_19_ALPHA_THERM, 0);
++ }
++ } else {
++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
++--- a/drivers/net/wireless/ath/ath9k/hw.c
+++++ b/drivers/net/wireless/ath/ath9k/hw.c
++@@ -901,7 +901,7 @@ static void ath9k_hw_init_interrupt_mask
++ AR_IMR_RXORN |
++ AR_IMR_BCNMISC;
++
++- if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
+++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
++ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
++
++ if (AR_SREV_9300_20_OR_LATER(ah)) {
++@@ -3104,6 +3104,7 @@ static struct {
++ { AR_SREV_VERSION_9462, "9462" },
++ { AR_SREV_VERSION_9550, "9550" },
++ { AR_SREV_VERSION_9565, "9565" },
+++ { AR_SREV_VERSION_9531, "9531" },
++ };
++
++ /* For devices with external radios */
++--- a/drivers/net/wireless/ath/ath9k/mac.c
+++++ b/drivers/net/wireless/ath/ath9k/mac.c
++@@ -837,7 +837,7 @@ void ath9k_hw_enable_interrupts(struct a
++ return;
++ }
++
++- if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
+++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
++ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
++
++ async_mask = AR_INTR_MAC_IRQ;