diff --git a/patches/openwrt/0012-add-patch-for-reset-retry-on-wdr3600.patch b/patches/openwrt/0012-add-patch-for-reset-retry-on-wdr3600.patch
deleted file mode 100644
index d8dfcdab57c9a6c97cfb17519bb73dda39dba1f3..0000000000000000000000000000000000000000
--- a/patches/openwrt/0012-add-patch-for-reset-retry-on-wdr3600.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From: Nico <github@nicoboehr.de>
-Date: Sat, 14 Dec 2024 22:41:57 +0000
-Subject: add patch for reset retry on wdr3600
-
-Signed-off-by: Nico <github@nicoboehr.de>
-
-diff --git a/target/linux/ath79/patches-5.15/940-ath79-reset-retry-wdr3400.patch b/target/linux/ath79/patches-5.15/940-ath79-reset-retry-wdr3400.patch
-new file mode 100644
-index 0000000000000000000000000000000000000000..a95d47f6495cc4ac67951e88bd8811ccffff5898
---- /dev/null
-+++ b/target/linux/ath79/patches-5.15/940-ath79-reset-retry-wdr3400.patch
-@@ -0,0 +1,16 @@
-+--- a/drivers/reset/reset-ath79.c
-++++ b/drivers/reset/reset-ath79.c
-+@@ -79,8 +79,12 @@ static int ath79_reset_restart_handler(s
-+ {
-+ 	struct ath79_reset *ath79_reset =
-+ 		container_of(nb, struct ath79_reset, restart_nb);
-++	unsigned int i = 0;
-+ 
-+-	ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
-++	while (1) {
-++		ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
-++		printk("reset: still alive after %u tries\n", i);
-++	}
-+ 
-+ 	return NOTIFY_DONE;
-+ }
diff --git a/patches/openwrt/0012-ath79-implement-reset-sequence-according-to-datasheet.patch b/patches/openwrt/0012-ath79-implement-reset-sequence-according-to-datasheet.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4f515a4d35d9ff73bc480d3364ad8a35a034ca7c
--- /dev/null
+++ b/patches/openwrt/0012-ath79-implement-reset-sequence-according-to-datasheet.patch
@@ -0,0 +1,93 @@
+From: Nico <github@nicoboehr.de>
+Date: Sun, 15 Dec 2024 15:18:18 +0000
+Subject: ath79: implement reset sequence according to datasheet
+
+The AR9344 datasheet specifies on p. 111 one should follow this
+sequence:
+
+- Read-modify-write bit 8 ETH_SWITCH_RESET
+- wait 1 msec
+- read-modify-write bit 12 ETH_SWITCH_ARESET
+- wait 1 msec
+- read modify write bit 24 FULL_CHIP_RESET
+
+Implement the sequence, note that this may break chips other than
+AR9344.
+
+diff --git a/target/linux/ath79/patches-5.15/940-ath79-fix-reset-sequence.patch b/target/linux/ath79/patches-5.15/940-ath79-fix-reset-sequence.patch
+new file mode 100644
+index 0000000000000000000000000000000000000000..dccb8449e9cc03701495afcbc4196540d0b1c15d
+--- /dev/null
++++ b/target/linux/ath79/patches-5.15/940-ath79-fix-reset-sequence.patch
+@@ -0,0 +1,71 @@
++--- a/drivers/reset/reset-ath79.c
+++++ b/drivers/reset/reset-ath79.c
++@@ -12,6 +12,8 @@
++ #include <linux/platform_device.h>
++ #include <linux/reset-controller.h>
++ #include <linux/reboot.h>
+++#include <linux/delay.h>
+++#include <linux/of.h>
++ 
++ struct ath79_reset {
++ 	struct reset_controller_dev rcdev;
++@@ -21,16 +23,13 @@ struct ath79_reset {
++ };
++ 
++ #define FULL_CHIP_RESET 24
+++#define ETH_SWITCH_RESET 8
+++#define ETH_SWITCH_ARESET 12
++ 
++-static int ath79_reset_update(struct reset_controller_dev *rcdev,
+++static void __ath79_reset_update_unlocked(struct ath79_reset *ath79_reset,
++ 			unsigned long id, bool assert)
++ {
++-	struct ath79_reset *ath79_reset =
++-		container_of(rcdev, struct ath79_reset, rcdev);
++-	unsigned long flags;
++ 	u32 val;
++-
++-	spin_lock_irqsave(&ath79_reset->lock, flags);
++ 	val = readl(ath79_reset->base);
++ 	if (assert)
++ 		val |= BIT(id);
++@@ -39,6 +38,17 @@ static int ath79_reset_update(struct res
++ 	writel(val, ath79_reset->base);
++ 	/* Flush cache */
++ 	readl(ath79_reset->base);
+++}
+++
+++static int ath79_reset_update(struct reset_controller_dev *rcdev,
+++			unsigned long id, bool assert)
+++{
+++	struct ath79_reset *ath79_reset =
+++		container_of(rcdev, struct ath79_reset, rcdev);
+++	unsigned long flags;
+++
+++	spin_lock_irqsave(&ath79_reset->lock, flags);
+++	__ath79_reset_update_unlocked(ath79_reset, id, assert);
++ 	spin_unlock_irqrestore(&ath79_reset->lock, flags);
++ 
++ 	return 0;
++@@ -79,8 +89,20 @@ static int ath79_reset_restart_handler(s
++ {
++ 	struct ath79_reset *ath79_reset =
++ 		container_of(nb, struct ath79_reset, restart_nb);
+++	unsigned long flags;
++ 
++-	ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
+++	spin_lock_irqsave(&ath79_reset->lock, flags);
+++	/* special reset sequence required for AR9344 - see datasheet p 111 */
+++	if (of_machine_is_compatible("qca,ar9344")) {
+++		__ath79_reset_update_unlocked(ath79_reset, ETH_SWITCH_RESET, true);
+++		mdelay(2);
+++		__ath79_reset_update_unlocked(ath79_reset, ETH_SWITCH_ARESET, true);
+++		mdelay(2);
+++		__ath79_reset_update_unlocked(ath79_reset, FULL_CHIP_RESET, true);
+++		mdelay(10);
+++	} else
+++		__ath79_reset_update_unlocked(ath79_reset, FULL_CHIP_RESET, true);
+++	spin_unlock_irqrestore(&ath79_reset->lock, flags);
++ 
++ 	return NOTIFY_DONE;
++ }